What is TIEOFF_X0Y31

Adam,

There are tie-off pins for the TEMAC, the 440PPC, and other blocks. Which tie-off is this associated with?

Austin

Adam,

OK, I opened up FPGA Editor, so I now think I know what you are asking.

Associated with each CLB, is an interconnect block. This block represents a convenient way to visualize the interconnection resources in the FPGA (the actual schematics, layout, and physical placement is entirely different).

This "switch box" has inputs and outputs. There is a little block to the right, and to the top of the switch box, which has some logic 0, and logic 1 points. These are identified as TIEOFF_X??Y??.KEEP1 or .KEEP0 (tie to 1, or tie to 0).

These are places where the synthesis may find a logic 1, or a logic 0, so as to tie a signal high, or low, as required (for example unused inputs to a function may be specifically directed to exist, not be trimmed no optimized, and thus need to go somewhere).

These tie off points represent a functional view of what is going on which is also not necessarily present, nor implemented in the same way as in the hardware itself.

Remember that FPGA Editor is a convenient way for the software people to reduce the complexity of the schematics to a functional view of the FPGA device: it is not a schematic, nor even a simplified schematic of the device.

Like many other items in FPGA Editor, this is almost 25 years old (!) and is considered "so obvious" that no one ever even thought about documenting it, or even explaining it.

I apologize,

Austin

chestnut wrote:

Austin,

thank you for your replies. it is crystal clear to me now. I always thought myself of a FPGA veteran until I went through your replies. there are still FPGA commonsense which are blind to me...

thank you again and have a good holiday,

Adam