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Re: What is the name of the circuit structure that generates a state machine's jumping signals?
On Sunday, December 23, 2018 at 8:58:36 AM UTC-5, Weng Tianxiang wrote:
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com wrote:
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:
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its:
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y were one-cycle logic.
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f 3 entities I have developed as a wave-pipelining circuit library.
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 determined wave-constants passing to the entity.
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into new HDL standard.
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-cycle logic, but other logic relating to the wave-pipelining parts are the
 same and classified into 3 categories that leads to 3 entities.
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timing analysis, what exactly do your libraries do?  What are your three en
tities?  
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ming of an FPGA circuit???  Timing is determined as much by the routing as  
it is the logic elements.  So it is up to the chip vendor's place and route
 tools to get that right.  This would not be an easy task to accomplish.  
  
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 as important as maximum delays in FPGA logic.  It is hard to tell if you c
ould ever get this to work across the three variables of timing, process, v
oltage and temperature.  Every chip will vary.  Each board with slightly di
fferent PS voltages will vary.  Every operating temperature will vary.  For
 a wave pipeline to work all of the inputs to the delay equation have to re
sult in a very small window of delay variation.  
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Nowadays every company has the technology. Based on my knowledge, even Chin
ese Huawei cellphone company uses the technology comfortably.
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he technology. Nowadays any variations of temperatures, routine delays and  
voltages are well known and calculated.

The 8087 is not an FPGA.  Nothing you have said addresses the fundamental l
imitations to using wave-pipelining in FPGAs.  It doesn't matter if you can
 calculate the delay variation from PVT or routing.  Knowing it isn't the p
roblem, controlling it is.  There is nothing the user can do about PVT so i
t is a variable that blurs the arrival time of the signal to the actual FF.
  When that blurring becomes wider than a clock cycle you have to slow the  
clock.  Processing variations will likely be the largest contributor and th
ere is nothing to be done about it until they start binning chips for a spe
ed range rather than just maximums.  

The other issue that has been pointed out to you is that in FPGAs there are
 typically an excess of FFs RIGHT NEXT to the LUTs.  So if you save FFs by  
wave-pipelining you have done little if anything.  Perhaps a small amount o
f power.  

  Rick C.

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  - Tesla referral code - https://ts.la/richard11209

Re: What is the name of the circuit structure that generates a state machine's jumping signals?
On 23/12/2018 06:33, snipped-for-privacy@gmail.com wrote:
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..

To do a bit of nitpicking, they do (have to for timing optimisations)  
and I am not talking about a wire-load model. High-end synthesis tool  
offer what is called Physical Aware Synthesis (PAS). What they do is to  
run an internal placer (or use the P&R vendors version) and use that to  
estimate the timing to a surprising degree of accuracy. Apparently they  
do not need to run the actual routing as this is not required for a good  
estimate.

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I would say that for modern FPGA's the routing is normally the timing  
killer (on my designs routing delay >2x logic delay). I guess this is  
the reason products like Plunify (no affiliation) are so successful.

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Regards,
Hans
www.ht-lab.com

Re: What is the name of the circuit structure that generates a state machine's jumping signals?
On Sunday, December 23, 2018 at 11:43:29 AM UTC-5, HT-Lab wrote:
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:
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timing analysis, what exactly do your libraries do?  What are your three en
tities?
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ming of an FPGA circuit???  
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I'd love to know more about that.  If they don't know the routing in the en
d design how can they know the timing?  I don't know how you would "estimat
e" the timing.  In particular, the timing required by wave-pipelining would
 be much more detailed than in regular design requiring limits on the minim
um AND maximum delays of *each path*, not just logic.  

I can't see how this would be possible, much less practical in any real wor
ld design other than regular structures like multipliers, etc.  


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.  This would not be an easy task to accomplish.
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 as important as maximum delays in FPGA logic.  It is hard to tell if you c
ould ever get this to work across the three variables of timing, process, v
oltage and temperature.  Every chip will vary.  Each board with slightly di
fferent PS voltages will vary.  Every operating temperature will vary.  For
 a wave pipeline to work all of the inputs to the delay equation have to re
sult in a very small window of delay variation. >
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  Rick C.

  + Get 6 months of free supercharging
  + Tesla referral code - https://ts.la/richard11209

Re: What is the name of the circuit structure that generates a state machine's jumping signals?
On 23/12/2018 17:56, snipped-for-privacy@gmail.com wrote:
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..

Unfortunately I don't have much info on this, perhaps somebody else on  
this ng knows how it all works. I suspect that placement will allow you  
to identified the long tracks and congested areas, a wire-load model can  
then be used for final bits.

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I agree, but I was not talking about wave-pipelining, just regular  
synthesis.

Regards,
Hans
www.ht-lab.com

Re: What is the name of the circuit structure that generates a state machine's jumping signals?
On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote:
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at the signal must appear during the synthesization.
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Again you are mistaken except for the special case of a one-hot encoded sin
gle input state machine.  Post the source code for something other than tha
t type of state machine that you have actually used along with the synthesi
s result that produces the S0_C1 signal to provide evidence otherwise you'r
e just making baseless, incorrect statements again.

Kevin

Re: What is the name of the circuit structure that generates a state machine's jumping signals?
On Saturday, December 22, 2018 at 5:43:51 PM UTC-5, Weng Tianxiang wrote:
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Even if the patents are useful they wouldn't make it into any language standard...because they are patented.  You don't understand how language standards happen, they are not going to take in anything claimed as proprietary.

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So you're saying that Google reviewed your patents and did not find any value for them as a company.  If the patents are so useful shouldn't you be mentioning which companies DID license your patents?

Kevin

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