What is the name of the circuit structure that generates a state machine's jumping signals?

:

rote:

e machine's jumping signals?

ered the structure name as "decision tree". By looking at Wikipedia, I real ize that it is a wrong name.

that can generate signal S0_C1 and others. I think it is an oldest circuit .

te machine?

1, et. al. exist at any point in this design. They may, but might not depe nding on the details of the state encoding and the optimizations performed. 1, et. al. are encoded in some manner. The actual logic generated would th en depend on all the input combinations that assert a given bit in the enco ded state values. So if the state variable WState_NS is three bits and use s 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_N S(1) would have another equation which is not likely to be the same.

state variable, but how likely is it that the software will optimize out th e exact signals you hypothesize?

ts"

hing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current c ycle based on the S0_C1 logic which I have given before.

signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any desig n tasks using this signal, but that does not mean it is in any way real. E ven in the case of a 1-hot encoded machine this signal will only exist if t here are no other ways to enter the state S1.

heoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world impl ementation or is in any way fundamental to the operation of the state machi ne.

at can > generate signal S0_C1 and others. I think it is an oldest circuit.

machine?

pes of decomposition, optimization and synthesis on it that are also used o n all the other logic code you use in the rest of your design.

g. In a month or so I will publish something that will show your following

2 claims are wrong:

xist if there are no other ways to enter the state S1.

lementation or is in any way fundamental to the operation of the state mach ine.

s merely an explanation." - Dale Carnegie

ach "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The act ual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into th is state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF migh t be an OR of S0_C1, S1_C1N, S2_something...

aw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or ot her logic device. The actual input to the state FF is what we call next_st ate and is not always equivalent to what you seem to be picturing. What yo u seem to be picturing can be used in design, but it may not be a real sign al in the implementation.

Sure, go for it. Have you ever done it? There are times when I know what logic I want in terms of the elements in the FPGA. Trying to get the tool to produce that logic can actually be hard. I'm not sure if Weng thinks th e tools will produce exactly what he is thinking or if he is thinking the s ignals he is talking about are somehow fundamental to the nature of a state machine. He won't say, likely because he thinks there is something to be patented there.

Yeah, he may get a patent, but it's not like it will be useful. I think he was the guy who came up with some fantastic idea of how to design wave pip eline architectures. We tried to explain to him that he appeared to be ove rsimplifying the matter and that time delay variance must be considered whe n constructing such designs.

He says he'll be back in a couple of months when he has his patent applied for and he can discuss the details.

Rick C.

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:

rote:

e machine's jumping signals?

ered the structure name as "decision tree". By looking at Wikipedia, I real ize that it is a wrong name.

that can generate signal S0_C1 and others. I think it is an oldest circuit .

te machine?

1, et. al. exist at any point in this design. They may, but might not depe nding on the details of the state encoding and the optimizations performed. 1, et. al. are encoded in some manner. The actual logic generated would th en depend on all the input combinations that assert a given bit in the enco ded state values. So if the state variable WState_NS is three bits and use s 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_N S(1) would have another equation which is not likely to be the same.

state variable, but how likely is it that the software will optimize out th e exact signals you hypothesize?

ts"

hing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current c ycle based on the S0_C1 logic which I have given before.

signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any desig n tasks using this signal, but that does not mean it is in any way real. E ven in the case of a 1-hot encoded machine this signal will only exist if t here are no other ways to enter the state S1.

heoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world impl ementation or is in any way fundamental to the operation of the state machi ne.

at can > generate signal S0_C1 and others. I think it is an oldest circuit.

machine?

pes of decomposition, optimization and synthesis on it that are also used o n all the other logic code you use in the rest of your design.

g. In a month or so I will publish something that will show your following

2 claims are wrong:

xist if there are no other ways to enter the state S1.

lementation or is in any way fundamental to the operation of the state mach ine.

s merely an explanation." - Dale Carnegie

ach "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The act ual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into th is state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF migh t be an OR of S0_C1, S1_C1N, S2_something...

aw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or ot her logic device. The actual input to the state FF is what we call next_st ate and is not always equivalent to what you seem to be picturing. What yo u seem to be picturing can be used in design, but it may not be a real sign al in the implementation.

Rick,

We don't have to argue, follow Dave's advice, take my code, compile it in X ilinx, look at the generated logic, you would find my S0_C1 signal is there , whether you have 10 states or 100 states.

Very simple thing can be solved by Dave's advice and facts, not by argument .

I have spent a lot of time reading the generated logic!

Weng

te:

e:

ate machine's jumping signals?

mbered the structure name as "decision tree". By looking at Wikipedia, I re alize that it is a wrong name.

od that can generate signal S0_C1 and others. I think it is an oldest circu it.

?

tate machine?

_C1, et. al. exist at any point in this design. They may, but might not de pending on the details of the state encoding and the optimizations performe d.

S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the en coded state values. So if the state variable WState_NS is three bits and u ses 00, 01 and 10 for the state values, the variable WState_NS(0) would hav e its own equation (I'll skip solving that for you) and the variable WState _NS(1) would have another equation which is not likely to be the same.

e state variable, but how likely is it that the software will optimize out the exact signals you hypothesize?

bits"

thing is: there is A BIT SIGNAL that will make the state machine going fro m state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before.

he signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any des ign tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1.

theoretical analysis, fine. I have found in certain cases decomposition t o similar basic signals to be useful in specifying state machines in a simp le way. But don't for a minute believe that it exists in any real world im plementation or is in any way fundamental to the operation of the state mac hine.

that can > generate signal S0_C1 and others. I think it is an oldest circui t.

e machine?

types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design.

ong. In a month or so I will publish something that will show your followin g 2 claims are wrong:

exist if there are no other ways to enter the state S1.

mplementation or is in any way fundamental to the operation of the state ma chine.

ems merely an explanation." - Dale Carnegie

each "hot" (state element) is it's next value. That value depends on *all

• the possible transitions into a given state, not just a transition from a ny one state into that state which is what your S0_C1 bit signal is. The a ctual signal at the input to the state FF is the logical OR of the equivale nt signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clo ck enable is also used, sometimes inefficiently. So the input to the FF mi ght be an OR of S0_C1, S1_C1N, S2_something...

draw diagrams, etc). My only point is this has nothing to do with the actu al resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_ state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real si gnal in the implementation.

Xilinx, look at the generated logic, you would find my S0_C1 signal is the re, whether you have 10 states or 100 states.

nt.

Where would I find your signal? This is your design, your claim. Have you synthesized the program (it won't compile as it is not complete).

else WState_NS

Xilinx, look at the generated logic, you would find my S0_C1 signal is the re, whether you have 10 states or 100 states.

Take that same code and compile it in Quartus and you will find no such S0_ C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four signal s: C1, Sini, WState.S0 and C2. The lookup table implements the following logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic imp lemented in the entire post-fit design.

In your earlier code posting you stated: Now a synthesizer must generate a signal S0_C1 as follows: S0_C1 I agree and I've posted my full set of facts. Perhaps you can be as fully descriptive using Xilinx tools.

If what you claim to see from Xilinx is true, you seem to have left out som e details. For example, while you say you see a signal "S0_C1

:

in Xilinx, look at the generated logic, you would find my S0_C1 signal is t here, whether you have 10 states or 100 states.

0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 wi th the 'D' input coming from lookup table logic. The output of the lookup is the next state of WState.S0. That lookup table takes as input four sign als: C1, Sini, WState.S0 and C2. The lookup table implements the followin g logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic i mplemented in the entire post-fit design.

a signal S0_C1 as follows: S0_C1

S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx ge nerates such a signal as you say, then it is doing so very inefficiently si nce, in order to generate the final next state input to the flip flop, ther e must be additional logic that you did not mention which will create addit ional delay and therefore lower performance. I find it hard to believe tha t a big brand like Xilinx would synthesize something as simple as you poste d so poorly. If it really does do as you say, then I'm even happier to be a user of Quartus rather than Xilinx...but again, I still highly doubt that brand X is that bad.

pping, and post-fitting. My description above is based on the post-fitting view, but none of the other views show a discrete signal to handle the tra nsition of S0 based on input C1.

ment.

y descriptive using Xilinx tools.

ome details. For example, while you say you see a signal "S0_C1

te:

t in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states.

S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 with the 'D' input coming from lookup table logic. The output of the looku p is the next state of WState.S0. That lookup table takes as input four si gnals: C1, Sini, WState.S0 and C2. The lookup table implements the follow ing logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic implemented in the entire post-fit design.

te a signal S0_C1 as follows: S0_C1 >

o S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx generates such a signal as you say, then it is doing so very inefficiently since, in order to generate the final next state input to the flip flop, th ere must be additional logic that you did not mention which will create add itional delay and therefore lower performance. I find it hard to believe t hat a big brand like Xilinx would synthesize something as simple as you pos ted so poorly. If it really does do as you say, then I'm even happier to b e a user of Quartus rather than Xilinx...but again, I still highly doubt th at brand X is that bad.

mapping, and post-fitting. My description above is based on the post-fitti ng view, but none of the other views show a discrete signal to handle the t ransition of S0 based on input C1.

gument.

lly descriptive using Xilinx tools.

some details. For example, while you say you see a signal "S0_C1

:

rote:

it in Xilinx, look at the generated logic, you would find my S0_C1 signal is there, whether you have 10 states or 100 states.

ch S0_C1 signal. Instead what you will see is a flip flop to hold WState.S

0 with the 'D' input coming from lookup table logic. The output of the loo kup is the next state of WState.S0. That lookup table takes as input four signals: C1, Sini, WState.S0 and C2. The lookup table implements the foll owing logic: not(Sini) and (C1 or C2 or WState.S0). There is no other log ic implemented in the entire post-fit design.

rate a signal S0_C1 as follows: S0_C1 > >

to S0 from input C1 as you have stated seeing when using Xilinx. If Xilin x generates such a signal as you say, then it is doing so very inefficientl y since, in order to generate the final next state input to the flip flop, there must be additional logic that you did not mention which will create a dditional delay and therefore lower performance. I find it hard to believe that a big brand like Xilinx would synthesize something as simple as you p osted so poorly. If it really does do as you say, then I'm even happier to be a user of Quartus rather than Xilinx...but again, I still highly doubt that brand X is that bad.

t-mapping, and post-fitting. My description above is based on the post-fit ting view, but none of the other views show a discrete signal to handle the transition of S0 based on input C1.

argument.

fully descriptive using Xilinx tools.

ut some details. For example, while you say you see a signal "S0_C1

Neither state S1 or S2 are not needed in order to implement your state machine that is functionally identical to any other implementation.

Kevin

On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, snipped-for-privacy@gmail.co m

Weng is upset that his original three state machine can actually be impleme nted with a single state. States 'S1' and 'S2' in that sense were cut off because they were useless.

at appeared to be an intermediate signal that may or may not exist in any g iven design, what are your questions exactly?

I don't think he has any actual questions. Weng tends to present claims th at tend to be false but insists they are true. That's his delusion to reso lve.

Weng also tends to post code that is not representative of the code that he bases his claim upon. That was the case here where he based his claim on code that did not have the "elsif C2" branch in it. Take that branch out a nd you have a one-hot encoded single input state machine which has already been pointed out to him to be the special case where his statement is in so me sense true. However, the 'S0_C1' signal that he crows about is really j ust the next state...so what?

Kevin

com

mented with a single state. States 'S1' and 'S2' in that sense were cut of f because they were useless.

what appeared to be an intermediate signal that may or may not exist in any given design, what are your questions exactly?

that tend to be false but insists they are true. That's his delusion to re solve.

he bases his claim upon. That was the case here where he based his claim o n code that did not have the "elsif C2" branch in it. Take that branch out and you have a one-hot encoded single input state machine which has alread y been pointed out to him to be the special case where his statement is in some sense true. However, the 'S0_C1' signal that he crows about is really just the next state...so what?

I will publish my research result in patent application form in a month or so, systematically describing a new tool every hardware engineer here will benefit from my invention, providing more than 10 circuits.

I don't see any benefits for continuing debates here.

Weng

Hello,

Am Donnerstag, 13. Dezember 2018 14:45:47 UTC+1 schrieb Weng Tianxiang:

s jumping signals?

transition (function) logic

Maybe it would be helpful for you to read en.wikipedia.org/wiki/Finite-state_machine

A FSM can be as simple as a counter from 0 to 1 (modulo 2) or can be a comp lete fpga design. It is often seen that someone claims this term only for " explicite expressed" FSMs using eg an enumerated type in VHDL, but in gener al all needed for a FSM is to have at 2+ states, any kind of input (clock a lone is sufficient) to activate switching between those states (based on a defined transition function) plus any output that is depending on state alo ne or state and input.

Especially the kind of coding structure used (1 process, 2 process, 3 proce ss) as well as the question if the states are enumerated type or std_logic_ vectors are not relevant.

You can draw a statemachine with bubble diagram which contains a bubble for each state and an arrow for each transition. In this abstraction you have a "signal" for each state transition.

Am Donnerstag, 13. Dezember 2018 14:45:47 UTC+1 schrieb Weng Tianxiang:

transition (function) logic

Maybe it would be helpful for you to read en.wikipedia.org/wiki/Finite-state_machine

A FSM can be as simple as a counter from 0 to 1 (modulo 2) or can be a comp lete fpga design. It is often seen that someone claims this term only for " explicite expressed" FSMs using eg an enumerated type in VHDL, but in gener al all needed for a FSM is to have at 2+ states, any kind of input (clock a lone is sufficient) to activate switching between those states (based on a defined transition function) plus any output that is depending on state alo ne or state and input.

Especially the kind of coding structure used (1 process, 2 process, 3 proce ss) as well as the question if the states are enumerated type or std_logic_ vectors are not relevant.

You can draw a statemachine with bubble diagram which contains a bubble for each state and an arrow for each transition. In this abstraction you have a "signal" for each state transition.

com

mented with a single state. States 'S1' and 'S2' in that sense were cut of f because they were useless.

what appeared to be an intermediate signal that may or may not exist in any given design, what are your questions exactly?

that tend to be false but insists they are true. That's his delusion to re solve.

he bases his claim upon. That was the case here where he based his claim o n code that did not have the "elsif C2" branch in it. Take that branch out and you have a one-hot encoded single input state machine which has alread y been pointed out to him to be the special case where his statement is in some sense true. However, the 'S0_C1' signal that he crows about is really just the next state...so what?

Isn't Weng the same guy who couldn't understand that for wave pipelining to work delays had to be bracketed rather than the max spec they give in FPGA s?

I seem to recall a fairly long argument about that fact. I wonder if he ev er got any sort of a patent out of that?

Rick C.

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Hi Thomas,

at the signal must appear during the synthesization.

ection for the offer on 2018/03/16, 7 months after they became patents.

I'm not interested in reading the patents. But if you wish to explain the point of your patents, the utility as it were, in a way that we can underst and, I would like to hear it. From the discussions we had you didn't under stand the futility of trying to use these patents in FPGAs. While they may be useful in ASICs, I don't believe you ever explained what you were actua lly patenting.

Rick C.

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Rick,

Here are the main points about my inventions on wave-pipelining circuits:

1. All wave-pipelining circuits will be written in such a code if they were one-cycle logic.

1. Use a link statement linking your wave-pipeling circuit with one of 3 entities I have developed as a wave-pipelining circuit library.

2. A synthesizer generates the wave-pipelined circuit with one or two determined wave-constants passing to the entity.

1. There is no other logic to write.

2. It is specially useful for FPGA if the new HDL rules are accepted into new HDL standard.

1. Theory base: all wave-pipelining circuits are different in their 1-cycle logic, but other logic relating to the wave-pipelining parts are the same and classified into 3 categories that leads to 3 entities.

2. Example circuits: FFT-16; floating A*B --> C;

Weng

re one-cycle logic.

entities I have developed as a wave-pipelining circuit library.

ermined wave-constants passing to the entity.

new HDL standard.

le logic, but other logic relating to the wave-pipelining parts are the sam e and classified into 3 categories that leads to 3 entities.

So what software handles the timing analysis and balances the delays???

If you are expecting the synthesis software to do the heavy lifting of timi ng analysis, what exactly do your libraries do? What are your three entiti es?

BTW, do you realize the synthesis software doesn't actually know the timing of an FPGA circuit??? Timing is determined as much by the routing as it i s the logic elements. So it is up to the chip vendor's place and route too ls to get that right. This would not be an easy task to accomplish.

And of course all of this ignores the fact that minimum delays are just as important as maximum delays in FPGA logic. It is hard to tell if you could ever get this to work across the three variables of timing, process, volta ge and temperature. Every chip will vary. Each board with slightly differ ent PS voltages will vary. Every operating temperature will vary. For a w ave pipeline to work all of the inputs to the delay equation have to result in a very small window of delay variation.

How do you plan to control any of that?

Rick C.

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s:

were one-cycle logic.

3 entities I have developed as a wave-pipelining circuit library.

etermined wave-constants passing to the entity.

to new HDL standard.

ycle logic, but other logic relating to the wave-pipelining parts are the s ame and classified into 3 categories that leads to 3 entities.

ming analysis, what exactly do your libraries do? What are your three enti ties?

ng of an FPGA circuit??? Timing is determined as much by the routing as it is the logic elements. So it is up to the chip vendor's place and route t ools to get that right. This would not be an easy task to accomplish.

s important as maximum delays in FPGA logic. It is hard to tell if you cou ld ever get this to work across the three variables of timing, process, vol tage and temperature. Every chip will vary. Each board with slightly diff erent PS voltages will vary. Every operating temperature will vary. For a wave pipeline to work all of the inputs to the delay equation have to resu lt in a very small window of delay variation.

Rick,

Intel first finished its 8087 chip using the wave-pipelining technology. No wadays every company has the technology. Based on my knowledge, even Chines e Huawei cellphone company uses the technology comfortably.

You are right that Xilinx and Altera also have the potential to control the technology. Nowadays any variations of temperatures, routine delays and vo ltages are well known and calculated.

Weng