What is MPGA?

Hi, I am wondering what's the difference between MPGA and FPGA? MPGA is Mask Programmed Gate Array. What does Mask mean here?

sincerely

------------- Kuan Zhou ECSE department

Reply to
Kuan Zhou
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A mask-programmable gate array uses one (or more) metal mask in the IC manufacturing process, to achieve the intended functionality.

In an FPGA, the user programs a standard off-the shelf chip, either by loading a bitstream into latches, or into Flash cells, or by programming antifuses. The manufacturer just provides software support. Peter Alfke

Reply to
Peter Alfke

If I remember this right, originally there were Gate Arrays, which were actually closer to transistor arrays. Everything needed to make logic circuits except the metal layer. (Maybe only one or two at the time.) NRE costs are lower than standard cell or custom logic, though usable density was a little lower, too.

Then along came FPGA's, so the original ones have been renamed?

-- glen

Reply to
glen herrmannsfeldt

I have run across the term "structured asic" these days but never really found a definition of it. Is structured asic simply what we used to call a gate array (fixed cell size cusomization of metal only)?

-Jeff

Reply to
Jeff Cunningham

Hi, Does it mean in MPGA the program process can be done only once, and it can only done on the foundry side?

sincerely

------------- Kuan Zhou ECSE department

Reply to
Kuan Zhou

Yes, and that's why FPGAs have become so popular. The user can make the change, and (except for antifuse FPGAs) the chip can be reprogrammed an unlimited number of times. Peter Alfke

Reply to
Peter Alfke

A structured ASIC requires only a subset of masks to customize. You might have two metal layers and 1 or two via layers for customization. This lowers NRE charges and improves turn around time. Equally important, structured ASICs take care of power distribution, clock distribution, test, and signal integrity issues via a combination of architecture and tools. There is also a lot of focus on accuracy of pre-handoff timing prediction based on placement so that the handoff is in one direction only. From a design tasks point of view it it similar to an FPGA. You obviously lose reprogramability, so if you like debugging live hardware, you will want to use one or more FPGAs to prototype.

Reply to
Ken McElvain

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