What is back_annotate?

Try using the Help menu, select index, search for back annotation.

Hope that gets you going in the right direction.

Alan

S> Hi, Dears:

I think I have sufficient knowledge in English, but still had troubles understanding what back-annotation is used for in Quartus II software. I have an assumption, that feature is designed to allow designer to compile certain piece of project the same way many times, even if you add some more functionality to the project.

Let's say, you created a module with very tight margins on setup/hold timings, frequencies, etc. Adding more functionality will definitely change the layout of the whole chip and may affect your critical block timings. To protect your critical part of design you may create a back-annotation file, which will guide Quartus II about exact way how to layout the module to achieve the same performance during next builds.

During my experiments I failed to get it work properly. Maybe I don't know how to read, or Quartus II help system omits some critical rules/restrictions. Don't understand the difference between this feature and LogicLock feature. For me, both are doing the same.

To Alan Myler: always hate people, who respond your way to the questions in the news-group. If you don't have to say anything about the topic, just ignore the post. You don't have to respond in the group if you don't like the question, neither obligated offend original poster.

With best regards, Vladimir S. MIrgorodsky

Alan Myler wrote:

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The backannotate command is useful if you want to do one of the = following:

1. If you do not have complete Pin Assignments (i.e. not speecified the = location of all your pins) and you want to use the ones that the Quartus = compiler has generated during fitting, then you should backannotate your = Pin and Device Assignments.

1. If your design is very close to complete, has critical timing paths = which need to be preserved and you plan on making very minor tweaks = only, use the backannotate Pin, Cell and Device Assignments. Use the = demote cells to AB or else you will overconstrain the fitter. If your = tweaks invalidate instance names created during the prior compile you = will get assignments that wil be ignored by the compiler.

2. Finally if your design is complete and you want to preserve routing = you may want to use backannotate Pin, Cell, Routing and Device = Assignments. Use this only if your design is complete. If you plan on = changing your logic remember to remove the cell and routing assignments = using the Assignment Editor, using the Category Locations. Do not remove = the pin assignments during this step, or else you will have to enterthem = again.

We recommend that customers mainly use Options 1 and 2.

Jude

Dear MIrgorodsky: After many experiments, I think the back-annotation command will copy the pin/LE/memory/PLL placements into the .qsf file as the location assignments, so after that you can see many location assignments in the Assignment Editor. Then if you re-compile the project, the location constraints will work and the Placement result will be the same.

For Incremental Compilation, the pro-fitting or pro-synthesis netlist will be kept so there is no need to back-annotate the assignments. But you can still use back-annotation with LogicLock feature, because LogicLock feature can not preserve the netlist or Fitting result.

Regards,

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