Apologies for posting in an FPGA group, but I couldn't think of a more appropriate one.
I hear ASIC designers talk about "full custom" designs. When I was at university our VLSI course painted colored polyons using Apollo workstations. I figure when you're laying down layers by hand, that's pretty custom.
These days though, it's all about RTL and constraints - all in text files (maybe aided by tools) and so when engineers talk about "full custom" I wonder what it actually means.
So I'd like a three minute synopsis on what a "full custom" work flow entails today. What are the engineers specifying and how are they specifying it?
Thanks, Paul.
(Feel free to use more than three minutes if necessary).
ASIC design (excluding FPGA designs) can be grouped into two categories: standard cell and full custom.
Standard cell designs use a cell library of logic gates of different sizes. The cells in this library are designed to be stacked together nicely in rows so that the power and ground connections match. For each logic gate (inv, nor, nand, etc.) several different sizes, or drive strengths are present. Usually these are named with the strength as a postscript representing the size of the transistors in the cell as compared to the minimum size. For example, an INV_4 is an inverter whose transistors are sized four times that of a minimum sized inverter. Software tools from such vendors as Cadence and Synopsys synthesis RTL to these standard logic cells, place these cells in rows and route them together, driven by constraints entered by the designer.
In full custom design, the designer sizes the transistors in each gate individually for maximum performance. This can entail 'pushing polygons' as you did in school under the guidance of circuit simulators and sizing tools, such as AMPS and Spice. Unlike standard cell design, where transistor widths are quantized, a designer can tailor each transistor's size to its specific load, reducing its input capacitance. Also, the designer can route wires and buses by hand for minimum delay and cross talk. In general full custom design takes much longer and respins are equally challenging. However, for designs where performance is paramount, such as a Pentium's ALU, full custom is what's used.
(Disclaimer: I used to be an ASIC designer where we did some semi-custom design, but I never taped-out any full custom designs.)
Please tell me the process involved. Is the ASICS are manufactured in the big manufacturing places like ordinary ICs. Or is there any way we can do it in our own lab. I am experianced only with FPGAs. Can we convert an RTL written for the FPGA to ASIC. Please suggest some books on this topic. Thank you.
A significant amount of time and expense is involved in making an ASIC. After the ASIC is taped out, masks have to be made and then it has to be manufactured. Modern mask sets can cost upwards of $1 million. The masks are then taken by the manufacturer and they oxidize, implant, anneal, etch, sputter, deposit and polish the wafers according to the various masks that they have.
You probably can't do ASIC manufacturing in your lab. ASIC fabs cost billions of dollars to make. It's not something you can do with salvaged parts of a flashlight and a toaster oven.
Also, I should mention that you need special tool sets to get an ASIC. You need to get ASIC synthesis tools (not terribly expensive, but still around $25k a seat as far as I understand), timing tools (primetime), layout and clock tree synthesis tools (astro, etc (very expensive)). These tools can easily cost millions of dollars. You also need to buy cell libraries. Artisan is a common developer of these.
As for your other question as to porting FPGA RTL to ASIC, yes it's possible as long as it is just RTL. Vendor primitives aren't supported. The problem with this is that RTL development is only part of the time expendature. I develop a small ASIC at work and timing closure is taking months. A big chip can take a really long time. A company I previously worked for (who developed VERY LARGE chips) would take 6+ months to do timing closure.
My suggestion would be to talk to Altera about Hard Copy. It is an FPGA to structured ASIC porting service. It is my understanding that they absorb a lot of the cost and you can do all of your development using their standard (couple thousand dollar) tools. You can also take a look at Xilinx EasyPath. They aren't ASICs, but they are a cheaper application specific FPGA option.
I can't suggest any really good books on it, because I've never seen a good book on this. I've learned it all through working with people who know it.
In the Leonardo spectrum there is a Device under the ASIC tab "SCL05U" whats that means ??. I thought it is some kind of device like FPGA in which we can implement the transistor kind of thing. I have searched through net for asic etc and saw an article desribing the structured asic and the platform asic whats the difference between that. The problem with me i am implementing a large design. But due to the inefficiency of the LUT based design of the FPGA i am only verifying a subset of the orginal design (in the Virtex2 XC8000). So how can i test the entire design before moving into the FAB and costly things ???
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