Hello,
I am using Xilinx ISE 7.1 and VHDL for a project deployed in a Virtex2 FPGA. I place&route and then I run the static timing analyzer. Results throw a timing constrain not met (see below). The weird thing is that it happens after I removed some logic from the project, without adding anything new. My understanding is that adding new logic could make place&route harder, but removing logic would give us more room to find a better allocation of resources. Any hints?
If it helps, related constrains are:
NET "gb_h3" DRIVE = 16 | SLEW = FAST ; NET "tim_clkin" TNM_NET = "tim_clkin"; TIMESPEC "ts_tim_clkin" = PERIOD "tim_clkin" 25 ns HIGH 50 %; offset = out 27ns after tim_clkin;
Timing Analyzer results (after and before removing the logic that brought the problem):
================================================================= Timing constraint: OFFSET = OUT 27 ns AFTER COMP "tim_clkin";
212 items analyzed, 31 timing errors detected. Minimum allowable offset is 30.044ns.-------------------------------------------------------------------------------- Slack: -3.044ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I875_Q3 (FF) Destination: gb_a (PAD) Source Clock: gb_h3_OBUF falling at 12.500ns Requirement: 27.000ns Data Path Delay: 6.103ns (Levels of Logic = 2) Clock Path Delay: 11.441ns (Levels of Logic = 3) Clock Uncertainty: 0.000ns Timing Improvement Wizard Clock Path: tim_clkin to i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I875_Q3 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tiopi 0.793 tim_clkin tim_clkin_IBUF net (fanout=1) 3.345 tim_clkin_IBUF Tbxxb 0.892 i_dsp_n0_i_global_bus_link_I_MUXCY_L net (fanout=1) 4.295 i_dsp_n0_i_global_bus_link_I_MUXCY_L/O Tgi0o 0.589 gb_h3_OBUF_BUFG net (fanout=94) 1.527 gb_h3_OBUF ---------------------------- --------------------------- Total 11.441ns (2.274ns logic, 9.167ns route) (19.9% logic, 80.1% route)
Data Path: i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I875_Q3 to gb_a Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tcko 0.568 i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I875_Q3 net (fanout=2) 0.289 i_dsp_n0_gb_addr_bus Tilo 0.439 i_dsp_n0_i_global_bus_link_GBADDR1 net (fanout=1) 1.164 gb_o_addr Tioop 3.643 gb_a_3_OBUFT gb_a ---------------------------- --------------------------- Total 6.103ns (4.650ns logic, 1.453ns route) (76.2% logic, 23.8% route)
================================================================== Timing constraint: OFFSET = OUT 27 ns AFTER COMP "tim_clkin";
212 items analyzed, 0 timing errors detected. Minimum allowable offset is 26.342ns.-------------------------------------------------------------------------------- Slack: 0.658ns (requirement - (clock arrival + clock path + data path + uncertainty)) Source: i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I876_Q6 (FF) Destination: gb_a (PAD) Source Clock: gb_h3_OBUF falling at 12.500ns Requirement: 27.000ns Data Path Delay: 7.233ns (Levels of Logic = 2) Clock Path Delay: 6.609ns (Levels of Logic = 3) Clock Uncertainty: 0.000ns
Clock Path: tim_clkin to i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I876_Q6 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tiopi 0.793 tim_clkin tim_clkin_IBUF net (fanout=1) 1.420 tim_clkin_IBUF Tbxxb 0.892 i_dsp_n0_i_global_bus_link_I_MUXCY_L net (fanout=1) 1.399 i_dsp_n0_i_global_bus_link_I_MUXCY_L/O Tgi0o 0.589 gb_h3_OBUF_BUFG net (fanout=93) 1.516 gb_h3_OBUF ---------------------------- --------------------------- Total 6.609ns (2.274ns logic, 4.335ns route) (34.4% logic, 65.6% route)
Data Path: i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I876_Q6 to gb_a Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tcko 0.568 i_dsp_n0_i_global_bus_link_i_GLOBAL_BUS_v241I876_Q6 net (fanout=2) 0.286 i_dsp_n0_gb_addr_bus Tilo 0.439 i_dsp_n0_i_global_bus_link_GBADDR1 net (fanout=1) 2.307 gb_o_addr Tioop 3.633 gb_a_22_OBUFT gb_a ---------------------------- --------------------------- Total 7.233ns (4.640ns logic, 2.593ns route) (64.2% logic, 35.8% route)