weird PACE Error, not one google result

I get the following error in PACE after starting "Assign Package Pins" in ISE 9.1 SP3: ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhdl' or 'verilog' keyword, found 'work'. It happens with a clean new project and a single top-level VHDL module and its constraint file. It seems that nobody encountered this issue before. Any ideas?

Reply to
mludwig
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Looks like you've included a .prj file into the project....

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

I got this error for every 9.1 project of mine, so I created a new project and added a single VHDL module (new). It has been made top module, and launched "Assign package pins" for it. Asked me, if I want to add a new ucf file to the design, answered yes and PACE opened, but with the error. ??? I am clueless.

Reply to
mludwig

Hello I get the same problem working with Spartan 3 and Virtex II Pro, it started when I was trying the ISE 9.1i Quick Start Tutorial (am new to ISE in general), when it comes to pin assigning the pins, PACE gives me this message: "PACE was unable to parse the HDL source file 'C:\...\counter.vhd' " and after that PACE shows this (whatever you call it):

Loading device for application Rf_Device from file '3s200.nph' in environmentC:\Xilinx91i. ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhdl' or 'verilog' keyword, found 'work'.

I searched and search, and the only result was this topic ... so I sent an Email to mludwig hoping that he knows by now an answer for this, but he didnt answer me :-( So I am trying to refresh the topic ... Thats all for the moment, thank you!

note: sorry for my bad English.

Reply to
Ligeti

The problem is in the pepExrtractor.prj file that ISE generates before calling Pace. I dont know what generates this file, but in a project that is OK the file does not exist. If you delete it, ISE just regenerates it. I am sure if you can fix the generation of this file all problems will go away! The contents of this file looks like:

work C:/Repository Working Copies/Link_Peak_and_Hold/ top_level_schematic.vhd

Notice the 'work' keyword it is complaining about at the start...

Reply to
ashes.man

OK HERE IS THE ANSWER ... IF THERE ARE SPACES IN THE DIRECTORY NAMES IN THE PATH THEN THIS PROBLEM AOCCURS. Make sure all directory names right back to the root directory have no spaces ... sheesh, that took some working out!!! Thanks for all the useful information on the diagnostic code xilinx!!!

Reply to
ashes.man

You are a genius. Thank you very much...I've spend the last 2 days pulling my hair out over that one. I was even about to throw my computer out the window at one stage....and I live on the 5th floor!!! You'ld think Xilinx would have more infomation about such a problem....thanks again though:)

Reply to
collinds104

Thank you so much. I've been trying fo hours to figure this one out. WHY isn't this mentioned anywhere by Xilinx...

Reply to
DomGiambo

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