Hi
I have several Spartan3 boards that have a very weird issue, namly when configured with one specific VHDL design using Impact with verify off then after first programming attempt (status fail with CRC check!) the JTAG chain is reported broken before the FPGA and further configuration or even jtag idcode reading is not possible until complete power off the FPGA. When imact option verify is on then however the same bitstream can be used to configure the boards multiply times, the JTAG lockup doesnt happen. It is not related to bad bitstream because the VHDL design (LEON3 system) when compiled to different FPGA (S3-1500 or s3-4000) has the same behaviour. The boards in question (2 different PCBs) seem to work with all other design I have tested.
To my understanding the JTAG TAP controller should be completly separate function block from the FPGA fabric - so no matter what is loaded as FPGA config should not make the JTAG TAP unscannable. So the issue could be only related to power supply behaviour, some voltage spike at FPGA startup?
Any ideas what to test or where to look? Or what to test. I would really like to get to the bottom of the problem and understand how come does LEON3 design make the JTAG Chain to die (this is what is looks like for the moment).
The FPGAs on the boards where I see this behaviour are with date codes mentioned in
but I dont think this could be the issue?
Antti