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Webpack sees 2 clocks when there is only one

Hello,

I'm implementing a data bus between a FPGA (XC2S100) and an 8051. Due to the multiplexed data/address bus I have to latch the 16 bit address on the falling edge of ALE (before the lower address byte is changed to the data byte) so I implement the latch easy enough, however when I sythesize it through the webpack it interprets this as a clock signal and gives me an error that it is connected to the wrong pin, it states that I should have it connected to a clock input. My question is how do I get the sythesizer to overlook this signal as a clock and treat it as a simple input.

Your help would be greatly appreciated.

In case you needed to see the snipit of code that I'm using to latch the data here it is (note I've also tried using ale_n'event and ale_n = '0' instead of faling_edge just in case the translation was somewhat messed up). This process latches the lower address byte into the signal address_low from the address_data bidirectional port on my entity.

... process(reset, ale_n) begin if reset = '1' then address_low '0'); elsif falling_edge(clk) then address_low

Reply to
Jason Berringer
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Hi Jason

Several choices, some more recommended than others!

1) Manually instance an IBUF component on the ale input. 2) XST specific attributes in the VHDL. 3) Options in XST

I'm a little rusty on my XST options and attributes, but I'm sure they can be found in the documentatin somewhere. However, they are obviously specific to XST and won't work with any of the other synthesis tools, such as Leonardo or Synplify. The manual IBUF definately works:

-- synopsys translate_off library unisim; use unisim.vcomponents.all;

-- synopsys translate_on entity whatever port (ale : in std_logic end entity;

architecture demo of whatever is signal ale_n:std_logic; component IBUF is port (I : in std_logic ; O : out std_logic); end component; begin--architecture

Manual_Buffer : IBUF(I => ale , O => ale_n);

end; --architecture

XST will produce a warning : "WARNING:NgdBuild:479 - The input pad net 'ale' is driving one or more clock loads that should only use a dedicated clock buffer. This could result in large clock skews on this net. Check whether the correct type of BUF is being used to drive the clock buffer."

HTH

Ian Poole

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Reply to
Ian Poole

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I'm a newbie myself, but I think you might want to take the ale_n out of the process parentheses.

Jim

Reply to
Jim

A couple of things:

1) You say you want a latch, so why the "falling_edge(clk)" clause?

2) Read the docs, they should tell you what to write to infer a latch. Probably something like:

process (ale, address_data) begin if (ale = '1') address_low

Reply to
Andy Peters

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The items in the parentheses are what is know as a sensitivity list, this means that anything listed (in the parentheses) will trigger the execution of the process. Removing ale_n from the sensitivity list will mean that this process will only execute when reset changes state, and will ignore ale_n. This is not the desired result. Ian's suggestion is probably the best way to get around this problem.

Reply to
Jason Berringer

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