Hello all,
This is a repeat from article 111605 from November 6-th to this group, see
The problem is that BRAM's are synthesized at first, and than later thrown away, but only if more than halve of the available BRAM resource are used! The problem described does NOT occur in WebPACK 7.1i, but DOES occur in everything after that, including the 9.1i application version J.30.
Does anyone has an ideas were to look? Please have a look at the problem description below.
Sietse Achterop Computing Science department University of Groningen, The Netherlands
================================ Here again the problem in short:
The design is the 8051-microcontroller, now version 1.5, with patches from
The design works perfectly OK in WebPACK version 7.1i04, so I would assume that something drastic as this should not happen. The VHDL code also works on Altera FPGAs. I am using Spartan3 here, and I'm using the linux version on Debian on Pentium IV.
The directory with the complete design is available at
The memory used is described in
In the synthesis report, mc8051_top.syr, under Low Level Synthesis the following lines appear, which are the only suspicious lines:
=========================== from mc8051_top.syr, line 887: INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed INFO:Xst:2399 - RAMs , are equivalent, second RAM is removed ============================= end of copy
If the inferred rams do not take half of the available BRAMs then these lines DO NOT appear and the generated design just works. Several 8051 programs are running perfectly, using data2mem and a bmm-file to fill the memory.
If the lines appear, the blockrams are largely REMOVED and the bitfile does not work at all.
Here a few fragments of the report: ========================================================================= Advanced HDL Synthesis Report
Macro Statistics # RAMs : 3 16384x8-bit single-port block RAM : 1 256x8-bit single-port block RAM : 1 8192x8-bit single-port block RAM : 1
=========================================================================
- Final Report * =========================================================================
...........
Cell Usage : .......... # RAMS : 4 # RAMB16_S1 : 3 # RAMB16_S9 : 1 # Clock Buffers : 2 # BUFG : 1 # BUFGP : 1 # IO Buffers : 74 # IBUF : 38 # OBUF : 36 # MULTs : 1 # MULT18X18 : 1 =========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 1520 out of 3584 42% Number of Slice Flip Flops: 597 out of 7168 8% Number of 4 input LUTs: 2894 out of 7168 40% Number of IOs: 75 Number of bonded IOBs: 75 out of 141 53% Number of BRAMs: 4 out of 16 25% Number of MULT18X18s: 1 out of 16 6% Number of GCLKs: 2 out of 8 25% ============================================================================
The number of BRAMs should we 13, as is inferred in the working WebPACK 7.1i version.