Warningmessage in ISE

Hi there

When I synthesis my design I get some warning messages.

A strange on is this:

It is declared in the Entity: entity RS232 is Port ( reset : in std_logic; clk : in STD_LOGIC; rx : in STD_LOGIC; PData : out STD_LOGIC_VECTOR (7 downto 0); PDataAcc : out STD_LOGIC); end RS232;

It is used in a process: SmallClkPros : process(clk, reset) begin ... ... end process SmallClkPros;

Why do I get this warning?

Raymond

Reply to
Raymond
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It simply means you are not using the signal in a synthesisable statement. Process signal enumerations are only relevant for simulation. Clock signals must be used in "if rising_edge(clk) then" statements to infer FFs in synthesis and extra conditions are used to infer clock-enable and mux logic.

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Daniel Sauvageau
moc.xortam@egavuasd
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Reply to
Daniel S.

I am going to assume that you have something in your process that uses clk. In that case, the next likely candidate is that the synthesis tool has found no outgoing signals in that process, that is, signals that connect to output pins, or signals that connect to signals that go to output pins, and has therefore been eliminated. I believe that causes this warning in Xilinx ISE.

Brad Smallridge aivision

Reply to
Brad Smallridge

Brad Smallridge skrev:

Actually, the process generates an other "controllable" clock that clocks an other process that has signals that is connected to other signals that in turn goes to output pins. (puh)

Raymond

Reply to
Raymond

I see that to run a process from an other process can be avoided (Like I do now) so I tried to put everything in the same process, same warnings.

////////////////////////// Warnings ////////////////////// WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. ////////////////////////////////////////////////////////////////

////////////////////////// CODE /////////////////////////// entity RS232 is Port ( reset : in std_logic; clk : in STD_LOGIC; rx : in STD_LOGIC; PData : out STD_LOGIC_VECTOR (7 downto 0); PDataAcc : out STD_LOGIC); end RS232;

architecture Behavioral of RS232 is

signal RPData : std_logic_vector(9 downto 0); signal CountReg : std_logic_vector(12 downto 0); signal SmallCountReg : std_logic_vector(3 downto 0); signal RPDataAcc : std_logic;

begin

SmallClkPros : process(clk, reset) begin if(reset

Reply to
Raymond

Reply to
Gerhard Hoffmann

Gerhard, Thank you Thank you Thank you :) :) :)

I have been completly blind!!!

Raymond

Reply to
Raymond

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