warning 1780 shown while synthesis, in xilinx 6.3i

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 I am designing a generic arbiter .
while synthesis the xilinx tool is giving warning

WARNING:Xst:646 - Signal <inter> is assigned but never used.
WARNING:Xst:1780 - Signal <k> is never used or assigned.

I searched  it out in the solution record
warning 646 can be ignored .
but warning 1780 is displayed in the case of jtag ,so i am not able to
conceive why this is coming.
i have pasted the design below.
thanks for help

 module  pri_encoder32(inbus,outbus);

  parameter size=9;
  parameter size_1=size-1;
  parameter size_out=4;
  input  [size-1:0]inbus;

  output reg  [size_out-1:0]outbus;

  reg [size_out-1:0]k;
  reg [size_out-1:0]inter;

    always @(inbus)
            for (k = size; k >= 1; k = k - 1)

                                  if (inbus[k-1]==1)
                                                 outbus = k-1;



Re: warning 1780 shown while synthesis, in xilinx 6.3i
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I'm not familiar with verilog, but it looks like this boils down to
k=1.  You may want to post this to comp.lang.verilog.
-Dave Pollum

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