want to pay for DCM active phase shift controller.

Hi all, I've been debugging my Active phase shift controller for so lon and I think it's time to ask for help. If you have done this and woul like to make some money, please reply me and let me know how much do yo want for it.

What I need is the state machine that control the DCM's psen, psclk psdone and locked....

please help. sincerely,

Reply to
cutemonster
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What types of problems are you having? You may want to try posting some code here to get some help. You may also want to mention which part you're using.

I've used the phase control on V4 and V2Pro parts and it doesn't seem to be all that hard to get to work.

John Providenza

Reply to
johnp

Yeah, post some code. This shouldn't be very hard. No offense, of course : )

I haven't used the dynamic phase shifting of the DCM, but I've used the DRP for the idelays and the MGT with no problems.

Reply to
motty

I've just been debugging mine (XCV2) ... In principle this is what I do:

A decrease phase until memory errors occur B increase phase until no errors, note phase (min value) C increase by a number of steps (i used 10) to get out of the edge region D increase phase until memory errors occur, note phase (max value) E set the phase to mid value.

All this assumes that I start of in the data eye, or below it. My problems so far were: C is needed, i.e. when leaving the unstable region you really need to take a safe step away from the edge. Secondly I discovered that dcm_status(0) i.e. ps overflow became set when scanning the phase upwards. So I changed "memory errors" to "memory errors OR dcm_status(0)". An early misstake I did was to assume PSDONE staying high, in reality (also stated in the manual) it just pulses for one cycle.

Hppe this helps, good luck /Pontus

Reply to
pontus.stenstrom

Here is my code, and please take a look and give me some advice. /* req_phase_y, phase_y_value, phase_y_sign[0] are I2c data received to start the phase change. After receive req_phase_y, req_phase_y_ack will be asserted. Wait until req_phase_y is clear, then proceed to state

8'h02. And state 3 and 4 is to send psen and receive psdone. The probe is psdone never asserted and phase shift never applied.

I feed CLKIN_IN(.clk4phaseChange) PSCLK_IN(.pixel_clk)

*/

always @ (posedge pixel_clk) begin if (rst) begin y_dynamic

Reply to
cutemonster

Here is my code, and please take a look and give me some advice. /* req_phase_y, phase_y_value, phase_y_sign[0] are I2c data received to start the phase change. After receive req_phase_y, req_phase_y_ack will be asserted. Wait until req_phase_y is clear, then proceed to state

8'h02. And state 3 and 4 is to send psen and receive psdone. The probe is psdone never asserted and phase shift never applied.

I feed CLKIN_IN(.clk4phaseChange) PSCLK_IN(.pixel_clk)

*/

always @ (posedge pixel_clk) begin if (rst) begin y_dynamic

Reply to
cutemonster

Honestly,

I thought you had a state machine that contolled the dynamic phase shifting only and that was the problem. This appears to be a design that has the dyanmic phase shift control inside of it and there could be multiple sources of error.

Dumb question, but have you simulated this? That is where I would start. This is too complicated to look at right now. I thought there was going to be some quick 'aha' code problem.

Reply to
motty

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