Wait-for / until won't work ? Xilinx Spartan 3

I usually write:

process (clk) begin -- process if rising_edge (clk) then -- Some code... end if; end process;

The "clk'event and clk = '1'" has always seemed to me to be a rather obtuse way of describing a rising edge when there is a perfectly good rising_edge function in std_logic_1164.

However, I'd agree that the process with "wait until rising_edge (clk)" is more clear for people that aren't familiar with the semantics of the sensitivity list.

Eric

IIRC, I heard of one user who had problems with an ASIC-style pad level library that transitioned from 0 to 1 via X. So if the designer used this pad for a clock pin, lets just say the simulation didn't quite work out as expected if rising_edge(clk) was used :) The ASIC vendor's recommendation was to use the clk'event style statements instead.

/Andreas

Many people's simulations involve multiple components, so what is or isn't true inside an FPGA/CPLD is not the whole story. As soon as you have an external pull-up on a line that might clock a FF (e.g. IIC) you're asking for trouble if you use the "clock'event and clock='1'" style.

I will conceed that this doesn't affect the majority of users. But it still makes for a nasty trap if you write code that someone else might use in a different context without delving into the internals to find out how your clock edges are detected.

As others have pointed out, they're also easier to read and make more sense to the uninitiated.

My apologies to non-VHDL programmers who are all no doubt wishing we would take this over to comp.lang.vhdl... :-)

Cheers,

-Ben-

I don't doubt your recollection; but if you're right, that's probably the silliest thing I've heard in a long time. At the very least the library vendor should have provided options to allow the X to be suppressed. The idea of an X appearing on a *clock* in sim is absurd.

It's even more absurd in Verilog, where you don't have the choice: @(posedge clock) gives you an event on BOTH 0->X and X->1. I'm sure that would have worked really well in gate-level sim :-)

Question:

Why is it not the best coding style? I've always been told that and have always stuck to if rising_edge(clk) then end if;

but you save a level of indent if you just put a wait until rising_edge(clk) at the top of your process. You can even put an if reset='1' at the end for you sync resets.

I assume it comes from the fact that in the old days synth tools didn't like it?

Cheers, Martin