To the FPGA Research Community,
We are pleased to announce the release of VTR 7.0. VTR is an open source f ramework for FPGA CAD and architecture exploration. The framework includes CAD tools that map Verilog/BLIF circuits to a user defined FPGA, benchmark s from a variety of applications/sources, sample FPGA architecture descript ion files, and scripts that tie these different components together.
What is new in VTR 7.0:
- Basic carry chain support through the whole CAD flow from elaboration dow n to routing.
- Power analysis
- Multi-clock timing analysis with support for simple SDC timing constraint s
- Architecture files that describe realistic, complex FPGAs with a reasonab le capture of area, delay, and power values
- Post-routed netlist support for timing-driven simulation
- Increased Verilog language support (eg. memory inferencing, support for p arameters)
- Verilog simulation and visualization for debugging
- Faster CAD algorithms
- Better quality of results for complex FPGA logic blocks
- Graphics for Windows
- Bug fixes and user friendliness improvements (Thank you to all users who provided us feedback on our first release of VTR)
The release may be downloaded here:
The VTR wiki and software trunk may be found here:
We hope that VTR will continue to aid your future research on FPGA architec ture and CAD.
From,
The VTR Development Team