1. Home
  2. Field-Programmable Gate Arrays
  3. VREF for SSTL out only / PCB

VREF for SSTL out only / PCB

Hallo,

in a hobby-design with Spartan3-200-TQ144 I wish to use DDR-RAM (Samsung SSTL2-25, max. 400MBit/s per IO, 32 Bit, 100Pins: K4D263238).

To save up DCI and VREF-lines, I declared one IO-Bank to be output only. Since I'm actually focussing on the HW, I'm unsure about wich IO-standard to select for this output-only bank (the xilinx datasheet reads a bit like "electing SSTL2 will require VREF pins, no matter of direction").

Furthermore, since this is my first PCB-layout, it'd be nice if=20 someone more experienced in PCB-design would give some hint=20 about it:

2-layer PCB, spartan on "blue", RAM on "red". Rambus on IO-Banks 1,2,3,6,7 (Bank 6 is out-only adress-Bus).=20

Nearly all rambus signals (only ~3 missing) are routed below the TQ144 chip, so there still seems to be room enough for the = power-rails outside the chip-scale on both layers.

Linelen.: 15 mm .. 21 mm (except BA0,1 lines [bottom 2 horizontal blue = lines]) LineInd.: 2.2nH .. 3.3nH (if I get this Software right)

formatting link

I'm unsure about the importance of further thinking about the rambus. Is board-impedance matching really an issue with 20mm / max.400 mbpps?

Gruss

Jan Bruns

Reply to
Jan Bruns
Loading thread data ...

no, but you will see a lot of inductive coupling in your design. Maybe you can add guard traces between you wires? Or simply spend the addtion 50$ for a multi layer board.

Kolja Sulimma

Reply to
Kolja Sulimma

Hi Jan, I like the way you've gone to all that effort to make the traces have equal length! I'm sure you've taken into account the different lengths of the signals in the lead-frames in both packages when doing this? Think about it, the electric travels about 2.54cm in 160ps. (your name sounds as though you'd prefer metric measurements! ;-)) At 400 Mbit/s each bit lasts for

2.5ns or about 40cm. How important do you think it is for all those signals to have exactly equal length? Cut yourself a little slack.

FWIW, given the two layer limitation, I would connect all the RAM pins straight through the board to the nearest FPGA pins, using whatever banks I had to. (Unless you have other reasons for bank selection?) Then flood under the RAM with a ground fill, and under the FPGA with Vccint. Via the FPGA grounds straight into the ground fill under the RAM. Vcco would be a ring around the outside of the FPGA. 1uF 0402 X5R decoupling caps for Vcco, Vccint, Vccaux inside this ring.

Anyway, good luck. Cheers, Syms.

Reply to
Symon

=20

mbpps?

Guard traces don't sem to help real much with this. Seems like I'll try to isolate not completly synchron signals.

Gruss

Jan Bruns

Reply to
Jan Bruns

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.