I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this.
Eddie
the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this.
Are you saying the supply rails of the device are +0.8 and -2.5V or that the logic level requirements are to swing from +0.8 (Vih_min) to -2.5V (Vil_max)?
How fast does the logic run?
What sort of latency can you live with?
Is there guaranteed AC content in the signal?
Some possibilities include capacitive level shifting, current-limited RS-232 drivers with diode clamps, low-voltage zener with a resistive pulldown...
If a couple of transistors can do the job, why not just use those? How many signals do you need to shift? Can you use arrays of transistors?
HTH, Gabor
Theere are some signals that are just static signals and do not need to run at high speed. There are other signals that act like SPI bus and may run at 25MHz. I do not that that can AC couple it as it is not a free running clock.
Eddie
the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this.
Is the load ECL? If so, look at the OnSemi TTL-to-ECL converter parts.
Or you could do it with opamps and a few resistors.
Or one common-base PNP and two resistors.
Or just two resistors.
John
John,
The load is is VCC referenced CML type. The positive rail is connected to 0.8V and VEE is connected to -2.5V. Do you think that I can use the TTL to ECL converter?
Thanks.
Eddie
the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this.
Is there any reason you can't simply run the target device with 2.5V on its ground rail? That would allow you to connect its +ve rail to 3.3V and its -ve rail to 0V.
- Brian
Brian,
I am sorry I am not able to understand your suggestion. I have the source device postive rail connected to 3.3V and negative rail connected to 0V. The source device generates TTL compatible signal. My real target device positive rail is connected to 0.8V and negative rail is connected -2.5V. Thus I can not not connecte the 3.3V TTL signal directly to the traget device and need to do the voltage translation.
I was thinking about using a device from analog device beween the source and target device at the following link.
Eddie
the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair of NPN and PNP transistors but would like to know if there is off the shelf device that can can do this.
Sounds like a 3 resistor solution to me. FWIR ECL biased like you describe, is symmetric about 0V, so you put a pull-down resistor to -2.5V to give the -ve ECL swing, and then ratio the resistors to give an equal positive ECL swing, and a resistor to GND allows the total swing to be reduced, and also to lower the drive impedance. Chuck it into spice, and solve iteratively.
-jg
Hi Eddie, I'm interested in where you ended up with such an awkward system? I wonder why the two sections cannot share a ground.
Anyway, download LTspice and load in the stuff below after saving it as 'level_shift.asc' or whatever. PNP and three resistors. Adjust the resistors to suit your voltage needs. You can get a full output range to the most negative rail.
HTH., Syms.
Version 4 SHEET 1 880 680 WIRE 176 48 -320 48 WIRE -320 80 -320 48 WIRE 176 112 176 48 WIRE 16 160 -16 160 WIRE 112 160 96 160 WIRE -80 176 -208 176 WIRE -208 208 -208 176 WIRE 176 240 176 208 WIRE 176 336 176 320 WIRE 256 336 176 336 WIRE 272 336 256 336 WIRE 176 352 176 336 WIRE 176 464 176 432 FLAG -80 208 0 FLAG -208 288 0 FLAG -320 160 0 FLAG 176 544 0 FLAG 256 336 Vout SYMBOL Digital\\buf -80 112 R0 WINDOW 3 0 0 Invisible 0 SYMATTR InstName A1 SYMATTR Value Vhigh=3.3 SYMBOL voltage -208 192 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 3.3 0 1n 1n 1u 2u) SYMBOL pnp 112 208 M180 SYMATTR InstName Q2 SYMBOL voltage -320 64 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 3.3 SYMBOL res 112 144 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 160 224 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 160 336 R0 SYMATTR InstName R3 SYMATTR Value 270 SYMBOL voltage 176 448 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value -2.5 TEXT -234 420 Left 0 !.tran 100us
device postive rail connected to 3.3V and negative rail connected to 0V. The source device generates TTL compatible signal. My real target device positive rail is connected to 0.8V and negative rail is connected -2.5V. Thus I can not not connecte the 3.3V TTL signal directly to the traget device and need to do the voltage translation.
target device at the following link.
and VEE is connected to -2.5V. Do you think that I can use the TTL to ECL converter?
Sounds nasty, given the +0.8 Vcc. Most of the translators assume a common 0v ground pin as both the TTL low and the ECL high.
how about....
fpga---------R1--------+--------cml input
0/3.3 | | R2 | | | | -2.5vwhich looks pretty good if R2 = 0.78 * R1
Does this have to be fast? Are the traces long? Those issues would affect the absolure values of the R's.
John
It needs to run at around 5 MHz. Yes the traces will be long about 24 inches or more.
Eddie
more.
Then to make it really clean, put the resistors near the FPGA and make R1 || R2 equal to the trace impedance, which will source-terminate the line.
I don't know which cml parts you're using, so check my math as regards levels.
John
or more.
Also see my earlier post, with a 3 resistor solution. That allows matching of signal-swing levels, and impedance, independently.
-jg
or more.
Right. That would likely result in less loading of the FPGA pin, too. He probably only needs 0.8 volts of swing, maybe less.
John
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