Vivado - Pack I/O Registers?

I get the following error message.

[Netlist 29-69] Cannot set property 'IOB', because the property does not exist for objects of type 'port'. ["C:/Users/pedro/Xilinx/artix_test/artix_test.srcs/constrs_1/new/top.xdc":7]

Here is my TCL constraints file so far. I just copied the syntax in UG912.

create_clock -period 5.000 -name clk -waveform {0.000 2.500} [get_ports clk] set_output_delay -clock [get_clocks clk] 4.000 [get_ports {led[0] led[1] led[2] led[3]}] set_input_delay -clock [get_clocks clk] 3.000 [get_ports enable] set_property IOB TRUE [get_ports {led[0] led[1] led[2] led[3]}]

:7]

You cannot set IOB on ports. You must do so on the FFs.

Jan

registers on inputs and outputs where possible. I have not been able to find that option in Vivado.

IOB is a property on registers so try setting it on the register you want to pack it to an IO location.

So it is back to 1985. I have to name all my registers or figure out what the synthesis tool calls them and hope they don't change names over time.

In Synopsys there was a trace back feature. You could trace ports to the nearest register then put the property on that. It was very indirect and often broke over time, generating very strange error messages.

Pete

Can't offer anything other than hoping Xilinx get's back to you with some sort of general solution. You're probably a month of so ahead of me in using Vivado. Disappointing if we have all sorts of whiz-bang new flows, but the most basic things like this just don't work.

I'd imagine there's gotta be some kind of way to wildcard it in the new tcl flows. Just be great if Xilinx would figure it out and show an example - for a feature that 99% of it's users will need.

--Mark

You can track the FFs from your ports using TCL commands in Vivado. I do not remember the exact syntax but you would use your original "get_ports" command as a parameter to another TCL command(s) to get your FFs for the "set_property" command.

I just checked my Vivado training materials and it seems you do not need to explicitly set IOB to TRUE on all the I/O FFs. The Vivado implementation does this automatically by default unless you disable it. You can disable it in the implementation settings using the "no_timing_driven" option of the "place_design" process.

Jan

I'm still looking for this option. I attended the intro Vivado training yesterday. The instructor told me there was an option under the Synthesis Settings menu but I cannot find it.

I will submit a feature request on the Xilinx WebCase system.