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Vivado MIG says "Design entry" is VERILOG, how to change to VHDL?

With Vivado 2015.4, I'm trying to add DDR3 memory to a Microblaze design. I add the Memory Interface Generator to the block diagram, and double-click on it to configure it. The windows that comes up says that "It is very impo rtant that the correct Vivado Project Options are selected", that Design En try is set to VERILOG (sic), and "If any of these options are incorrect, pl ease click on 'Cancel', change the Vivado Project Options, and restart MIG. However, the Vivado Project Options shows that my target language is VHDL . What do I actually have to do to convince MIG that Design Entry is VHDL?

Reply to
Eric Smith
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You might want to ask this on the Xilinx forums. I know that in Vivado many cores no longer come with multi-language support, but I'm still working mainly with ISE so I'm not sure whether MIG is one of those. Basically what I'm saying is that some cores now support only Verilog and some support only VHDL. This can become a headache if you use a third-party simulator with single-language support.

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Gabor
Reply to
GaborSzakacs

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