Vitrex5 JTAG capture and debug

Hi,

I'm currently implementing a design with a fairly large amount of static configuration data. It would be good to be able to capture the values of the registers in the FPGA and verify that they are being setup correctly. I could do this with chipscope, but there are so many registers it wouldn't leave much space for debugging of dynamic signals.

After a bit of research I've found that it is possible to capture the registers and (somehow) read them back and using the .ll file (somehow) figure out the value for each net.

Is anyone aware of an existing tool that can do this, or has any advice?

cheers Rob

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Rob
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just to clarify, I'm talking here about using the JTAG readback capture feature on a Virtex-5 FPGA.

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Rob

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