Hi,
in one the last posts Christos recommended me to use Virtual Pins if I want the Fitter not to optimize registered unused signals away.
I have a module "sie.vhd" instantiated in my top level schematic design file "top_d.vhd".
The module "sie.vhd" has a port "Eop_not_recog" of type std_logic. It is a registered signal which is not used at all.
(I use Altera QuartusII v 4.2).
In the Assignment Editor under LOGIC OPTIONS --> ADVANCED I define a Virtual Pin by going to the NODE FINDER and selecting the signal "Eop_not_recog" of the entity "sie.vhd" with the filter "Register : pre-synthesis". Then I select ASSIGNMENT NAME=Virtual Pin, VALUE=On, ENABLED=Yes
After compilation I go into the NODE FINDER again to see if "Eop_not_recog" is still listed with the filter "Registers : post-fitting", but it is not. I conclude from this that the fitter optimized the node away although I defined the node as a Virtual pin.
Can someone explain to me what went wrong?
Thank you for your help.
Rgds