[VirtexII + DCM + newbie] problems with the clocksignals from DCM

This is right out of the "Language Templates" found under the "Edit" menu:

-- D Flip Flop with Clock Enable

-- CLK: in STD_LOGIC;

-- ENABLE: in STD_LOGIC;

-- DIN: in STD_LOGIC;

-- DOUT: out STD_LOGIC;

process (CLK) begin if (CLK'event and CLK='1') then if (ENABLE='1') then DOUT

One possibility is to use the BUFGMUX primitive to switch between idle and active. I haven't used it for this purpose yet myself, so be *sure* to read the Libraries Guide entry on the BUFGMUX in the online SW Manuals. There may be a design issue if one of the two clocks in the BUFGMUX is inactive, so do your homework before just trying it out.

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Agreed, it is not good FPGA design.

But the crazy thing is that Xilinx has the ability to do this relatively safely... but they don't seem to push it very hard and the tools don't automatically use it for you. Check out the BUFGCE in the V2 and S3 devices.

Not portable, but usable.

Marc

If you know what you are doing, sure. Like most things, there's a rule and then reasons to break it.

-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian

To send private email:

you're right it is a bad design, but like i mentioned in my subject, i'm just a newbie getting to know VHDL and FPGA's...

thanx for the tips ... found some good info (not only concering this problem) ... so thanx for your answer!

kind regards

i'll check it out ... thanx for the tip

kind regards,

To be sure it went across correctly, I wasn't criticizing you personally...just wanted to stress that this isn't a good idea in general.

Think hardware design without an FPGA. Most of the same rules apply.

A clock mux on a V2 will switch between clocks cleanly. That's a resource you can use. However, you need to have the right reasons to do so. If it's simply to keep a FF from latching an input, it's probably safe to say that this would be a bad idea.

Yes, i know ;-) ... just wanted to stress that fact hehe ...

indeed indeed, i think the main problem was getting used to the fact that VHDL is a programming language but it designs hardware. so you tend to think to much in a software way, but i'm learning not to :-)

it's

i couldn't use the solution with the ce FF because the system clock is on the same clock as on of the output clock signals from the DCM so that would have divided the frequency by 2. but i looked at the BUFGCE component and that seems to have solved the problem (warning) but i'm still looking if the BUFGMUX. but for now the BUFGCE seems to be the solution ...

thanx, for the comments and help,

kind regards,

Yttrium

Well, technically it is an HDL ... "Hardware Description Language". The trick is to not think "sofware" at all and think that you are describing hardware constructs. That alone should keep you honest.

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I'm not sure I follow this without having more context in terms of what the design is attempting to do.