VirtexII bitstream relocation

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Hi all

I have questions about bitstream relocation in VirtexII FPGAs. We have
already developed software based on the old Jbits package from Xilinx
for doing small bits manipualations bitstream relacation for Virtex
devices, but we are facing difficulties in finding documentation about
how to perform significant-size IP-core bitstreams (50,000 gates or
more)
relocation in VirtexII devices. Can you give some hint on where such
documentation can be found, if it exists?

We are implementing a configurations controller manager in hardware,
to allow automated swap of IPs in a number of identical size
reconfigurable areas defined using the Modular Design flow (even
though the current documentation suggests that it is complicated to
make things work with more than one reconfigurable area at the same
time, we have managed to define and "almost" use 2 such areas).
The idea is: given a temporal schedule for reconfigurable IPs and
apply this using the ICAP interface to partially reconfigure the
device in one of the areas. Having more than one area is fundamental
to allow bitstream prefetch for hiding reconfiguration latency.

Thanks in advance for any help.

Ewerson L. S. Carvalho, Master Student - Informatics Institute, PUCRS
Mail Address: Av Ipiranga, 6681, Prédio 16. Porto Alegre, RS, Brazil
CEP:90619-900 - Phone:+55 51 3320 3611 - Fax:+55 51 3320 3758
e-mail: snipped-for-privacy@inf.pucrs.br - URL:
http://www.inf.pucrs.br/~ecarvalho

Re: VirtexII bitstream relocation
snipped-for-privacy@inf.pucrs.br (Ewerson Carvalho) wrote in message

Hi,
Take a look at: http://www.xilinx.com/xapp/xapp290.pdf
The flow described there recommends no more than one reconfigurable
module, but allows more than one.
They also have a flow for minor changes - such as RAM contents and
things like that.
Gilad.

Re: VirtexII bitstream relocation
gilad snipped-for-privacy@walla.co.il (Gilad Cohen) wrote in message
Quoted text here. Click to load it

Hi,

I have already developed sytems according to Modular Design based on
xapp290 with only one reconfigurable module, using Bus Macros. My
doubt is how can I relocate bitstreams on FPGAs? The difference
between two bitstrems with the same logic and designed to different
places is only CRC, FAR and FDR (bitstreams registers)? I don't know
if this is true.

Thanks in advance for any help.

Ewerson L. S. Carvalho, Master Student - Informatics Institute, PUCRS
Mail Address: Av Ipiranga, 6681, Prédio 16. Porto Alegre, RS, Brazil
CEP:90619-900 - Phone:+55 51 3320 3611 - Fax:+55 51 3320 3758
e-mail: snipped-for-privacy@inf.pucrs.br - URL:
http://www.inf.pucrs.br/~ecarvalho

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