Xilinx claimed that VirtexE DLL locks with input range 60-130 MHZ, my question is what's output clock limitation? Suppose I have 25MHz input clock, the CLKDV will be 12.5MHZ? Does it violate anyhting?
- posted
20 years ago
VirtexE DLL locked range
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- posted
20 years ago
The output clock of CLK0 is exactly the same as the CLKIN.
CLKDV can be any value as listed (1.5, 2, 2.5, 3, 4.....) (divisor of CLKIN).
So if CLKDV=2 (divide by two) everything is legal for a CLKIN of 25 MHz.
Aust> Xilinx claimed that VirtexE DLL locks with input range 60-130 MHZ, my