I used the ISE 9.2 MIG to create a DDR2 mem controller for 267MHz memory chips, and it included a DCM to generate the 267MHz clock at 0 and 90 degrees, from an external 267MHz input.
In my app, I have a 100MHz external input clock (low jitter), and I need four internal clocks: CLK0: 100MHz with zero skew re the input clock CLK1: 200MHz for IDELAYCTRL CLK2: 267MHz 0 degrees for DDR2 CLK3: 267MHz 90 degrees for DDR2
It seems that I can generate all of these with one PLL. The V5 User's Guide UG190 seems to recommend routing CLKFBOUT through a BUFG to CLKFBIN (fig 3-10). Or I think I could use the CLK0 BUFG output as the CLKFBIN signal, and save a BUFG by not using CLKFBOUT.
Is there any reason to prefer CLKFBOUT over CLK0 to get zero skew? Are CLK2 and CLK3 going to be fine for the MIG DDR2 controller? Is the PLL's 90 degree difference just as accurate as that of a DCM?
Thanks, Barry