Virtex5 not for SONET or SDH

Hey guys, Be careful when using Virtex5 for SONET. The RocketIO tile only has 1 PLL used for transmit and receive on both bidirectional ports. This PLL is normally sync'd to the local reference so the transmit data is on the local clock rather than the network clock (recovered clock). This architecture leads to all sorts of problems. Xilinx is recommending that a crystal controlled VCO oscillator be used for the local reference per XAPP649 (old Virtex2 app note) but this entails designing a phase comparator and analog filter. Even if you do this, your stuck with the second transmitter sync'd to the recovered clock of the first port. In our application we would like to use the second port for Ethernet in a POS application (can't be done). In order to make this work, the application software has to keep track of where the recovered clock is coming from and the clocks from several ports need to be muxed to select which recovered clock is used for the VCO reference. See what I mean?

Reply to
hemulliken
Loading thread data ...

I think your advice is basically sound, but...

I would extend it to say that ANY SONET/SDH application requires a LOT OF WORK.

Virtex 5 has a characterization report for OC-48, but it covers only the basic electrical and performance requirements: there is a lot more to SONET/SDH than just the transmit jitter, and the receive jitter tolerance (although, these are two very important specifications).

Clocking (or in SONET/SDH language - "synchronization and timing") is a huge issue, that requires careful design and architecture analysis to be able to meet the requirements of the end application. All the clocking modes, stratum levels, etc. go far beyond the basic MGT in a device.

We have an applications note on this subject, too:

formatting link

So, yes, the use of one PLL for both transmit and receive in order to save power in the MGT causes additional complexity for some, but overall, the power savings is well appreciated and becoming more important to telecom every day.

So, again, YES. Read the data sheets. Read the characterization reports. Talk to your Xilinx or disti FAE. Find all reference designs. Then, go to work and see how to (or if you can) use Virtex 5 to solve your problem.

Austin

Reply to
austin

I think you are correct to some extent.

I have used Virtex5, for SDH/Sonet application successfully for OC3/ OC12/OC48. And in general clocking is very complicated for SDH Sonet networks. You need to transmit each interface at system clock, which needs to have stratum3 (or 3E) specifications, with all the holdover capability. So you do need to use external PLL, which can satisfy all this specs. (i.e Zarlink). So once you have this PLL, then you can give this clock to transmit PLL of GTP.

I know the Transmit PLL sharing makes it little difficult, especially if you want to enable loopback, but I guess you can find work arounds for it. It has advantages because PLL being shared, saves power which can be a big factor in doing multiple interfaces designs.

Also another thing to note is that, since SONET/SDH does not require

8B/10B encoding, you could just do the receive part using the GTP, but the transmit part can be implemented using normal IOs for up to OC12 interface.

-- Goli

Reply to
Goli

Goli,

Thanks for the post. SONET/SDH is not for the faint of heart! I know we have many designs out their with V5 that ARE doing SONET/SDH, but that doesn't mean they are "easy" or do not require some other somewhat difficult circuits/tricks/techniques.

The timing issue is one that plagues ALL SONET/SDH solutions, and is in no way unique to Xilinx.

I spent 7 years on the ANSI/ATTIS committees that were responsible for synchronization standards of SONET. I at least tried to make it work, in spite of the crazy thinking. If we had it all to do over again, I am sure we would not have created such a synchronous mess: the old asynchronous digital hierarchy worked so well, and was so simple (in retrospect).

The very first meeting started with "we shall make it entirely synchronous, because integrated circuits are expensive, difficult to design and make, and we must use the fewest transistors possible." That seems completely stupid today! A good indication why the "old" phone companies became obsolete -- modern market forces and the advancement of technology left them all in the dust (literally).

The shared PLL is a "feature" of V5, and as noted, does make the design more difficult, but not impossible.

Austin

Reply to
austin

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.