Virtex5 DCM lower limit

try using higher clock and clock-enable "tick pulses" then you have now scew :)

Antti Lukats

My First Flash FPGA:

Here's a related vhdl example using clock enables: A counts every clock, B counts when A rolls, C counts when B rolls

-- Mike Treseler

The first question might be: Why do you need these clocks and what are you trying to do with them?

If you have data running at those rates, you can simply repeat data to make it update at the desired rate.

To exagerate, with a 100MHz clock you would need to repeat each word

1000 times to get an output that changes at a 100KHz rate. Similar math for the other rates.

A long time ago in school my APL professor (not a very common language today) insisted that the most important task before approaching a project was to really think about the representation of the problem. The same problem can either become very complex or very simple depending on the representation.

-Martin

First, Thanks for all your anwers.

In fact, I have to use the verilog core sources of a processor (originaly developped for silicium). The problem is the processor is made of latchs, internal tristate buses, and keepers which keep values on buses when there are not active drivers. More precisely, the core runs using two 180=B0 clocks with a nonoverlap time between the two, and during this time, the keepers assume that the last value is kept on the bus, that avoids hold violations. But in the FPGA, there are not any internal keepers, so I use my master clock (used to generate the two previous clocks) for reclocking critical tristate buses and to drive them during non overlap time.. The problem, I think, is like I create the two clocks using master clock, a counter, and a comparator, I create a delay between master clock edge and the others clocks edge, and like I reclock data generated on first two clocks with the master clock, I've a path between the two clock domains (which in fact are the same..) That's why I'm looking for generating the two 180=B0 clocks on an other way, for reducing delay between them and master clock.

Thanks for your comments and idea..

Best regards, Michel.

I believe Regional clock buffers in V5 have divider functionality available......so use DCM to generate Mhz clocks and then pass lowest mhz clock to a Regional clock buffer in divider mode and you have clocks with minimum skew. only thing you would need two regional clock buffers to avoid cumilative skew on 100khz clock

In Virtex 5's, the minimum output frequency that a DCM can output is

32Mhz and the minimum output frequency that a PLL can output is 19Mhz (this info is from one of the V5 guide's)

I have had this issue where in my DCM was getting locked intermittently when I was trying to output a 30Mhz clock from a DCM.

Hope this info helps..

--parag

Hi, and thanks for all your answers..

In fact, I had a lot of problem on this design for several month.. All my problems are due to the structure of the processor which seems to be asynchronous, uses keepers and tristates..

So, at the end of the last week, ( and thanks to Martin : "[...] the most important task before approaching a project was to really think about the representation of the problem [...]"), I decide to take two weeks to try something I thought since a long time : convert this strange design in full synchronous FPGA design.. You are going to tell me why didn't you do it before ?? and you should be right.. but this was due to the among of modifications required ( modify all the source files of the processor.. ) and the risk to obtain differents results from the original on silicium processor.. because the purpose of my design is to emulate the original processor..

So, thanks for your advices,

Best regards, Michel.

You are on the right path. Extract the requirements from the old design, then make it your own with portable, synchronous hdl code. Use an rtl viewer and simulation to check your work.

-- Mike Treseler