virtex4 reconfiguration time

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Fcclk max = 100 MHz

bitstream of VLX25 = 7.4 Mbit

SelectMAP port width = 32 bits

so the minimum reconfiguration time for this part should be a little bit
more than 7.4/100/32 = 2.3ms

correct?

Is the same CCLK freq sustainable thru ICAP?

Thanks

Re: virtex4 reconfiguration time

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NO, 8 bits

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NO, see above

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usually is ICAP way slower than max CCLK

Antti



Re: virtex4 reconfiguration time
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I don't agree with you: here are the 32 configuration data bits:

PAD209        X27Y127     IOB_X1Y127        F14    1    IO_L1P_D31_LC_1
PAD210        X27Y126     IOB_X1Y126        F13    1    IO_L1N_D30_LC_1
PAD211        X27Y125     IOB_X1Y125        F12    1    IO_L2P_D29_LC_1
PAD212        X27Y124     IOB_X1Y124        F11    1    IO_L2N_D28_LC_1
PAD213        X27Y123     IOB_X1Y123        F16    1    IO_L3P_D27_LC_1
PAD214        X27Y122     IOB_X1Y122        F15    1    IO_L3N_D26_LC_1
PAD215        X27Y121     IOB_X1Y121        D14    1    IO_L4P_D25_LC_1
PAD216        X27Y120     IOB_X1Y120        D13    1    IO_L4N_D24_VREF_LC_1
PAD217        X27Y119     IOB_X1Y119        D15    1    IO_L5P_D23_LC_1
PAD218        X27Y118     IOB_X1Y118        E14    1    IO_L5N_D22_LC_1
PAD219        X27Y117     IOB_X1Y117        C11    1    IO_L6P_D21_LC_1
PAD220        X27Y116     IOB_X1Y116        D11    1    IO_L6N_D20_LC_1
PAD221        X27Y115     IOB_X1Y115        D16    1    IO_L7P_D19_LC_1
PAD222        X27Y114     IOB_X1Y114        C16    1    IO_L7N_D18_LC_1
PAD223        X27Y113     IOB_X1Y113        E13    1    IO_L8P_D17_CC_LC_1
PAD224        X27Y112     IOB_X1Y112        D12    1    IO_L8N_D16_CC_LC_1
PAD225        X27Y79      IOB_X1Y79        AA14    2    IO_L1P_D15_CC_LC_2
PAD226        X27Y78      IOB_X1Y78        AB14    2    IO_L1N_D14_CC_LC_2
PAD227        X27Y77      IOB_X1Y77        AC12    2    IO_L2P_D13_LC_2
PAD228        X27Y76      IOB_X1Y76        AC11    2    IO_L2N_D12_LC_2
PAD229        X27Y75      IOB_X1Y75        AA16    2    IO_L3P_D11_LC_2
PAD230        X27Y74      IOB_X1Y74        AA15    2    IO_L3N_D10_LC_2
PAD231        X27Y73      IOB_X1Y73        AB13    2    IO_L4P_D9_LC_2
PAD232        X27Y72      IOB_X1Y72        AA13    2    IO_L4N_D8_VREF_LC_2
PAD233        X27Y71      IOB_X1Y71        AC14    2    IO_L5P_D7_LC_2
PAD234        X27Y70      IOB_X1Y70        AD14    2    IO_L5N_D6_LC_2
PAD235        X27Y69      IOB_X1Y69        AA12    2    IO_L6P_D5_LC_2
PAD236        X27Y68      IOB_X1Y68        AA11    2    IO_L6N_D4_LC_2
PAD237        X27Y67      IOB_X1Y67        AC16    2    IO_L7P_D3_LC_2
PAD238        X27Y66      IOB_X1Y66        AC15    2    IO_L7N_D2_LC_2
PAD239        X27Y65      IOB_X1Y65        AC13    2    IO_L8P_D1_LC_2
PAD240        X27Y64      IOB_X1Y64        AD13    2    IO_L8N_D0_LC_2

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Very interesting! Any figure?

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Re: virtex4 reconfiguration time

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those are Local Clock, the SelectMAP is 8 bit wide !!!!


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there is very little numbers on V4 ICAP but usually the ICAP is way slower
than selectmap, reason unknown

antti





Re: virtex4 reconfiguration time

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Actually the OP is correct - that IS supposed to be a 32-bit SelectMAP
interface... the ug075.pdf pinout document discusses it briefly.  I
don't blame everone for being confused about it though - Xilinx makes
just enough mention of it that you wonder if it might work, but when I
asked my trusty FAE about it a few months ago, he said it is not
supported at this time.

Also, _LC pins are Low Capacitance pins (can't do LVDS output).  Local
clock pins are called _CC (for Clock Capable).  Global clocks are
thankfully _GC.

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little bit

7.4/100/8 = 9.25 ms, plus a little at the beginning and end.  I'd
budget at least 10ms, maybe a few more.

Have fun!

   Marc


Re: virtex4 reconfiguration time
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wopla! I did see the paramter of bus width on the ICAP V4, but in ALL DOCs
the selectmap is defined as 8 bit, that is on ALL DOCs except the pinouts
docs!

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ah I was looking at the list of pins that contained _LC and _CC mixture so I
messed the two

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Re: virtex4 reconfiguration time
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Thank you guys for your feedback!

I am to understand that a 32b selectMap is reserved for future use, when
  7.1i will be stable, and xilinx engineers more available...

Ok, but how can the internal conf logic detect what is the kind of
incoming bistream? As soon as the syncro words? In that case, one can
not place any garbage on D[31..8], as they might be badly interpreted!


Actually, I was puzzled by this recent xilinx answer:

7.1i ECS - Bus width of pin I and O is incorrect in symbol ICAP_VIRTEX4

    
  Family: Software
  Product Line: FPGA Implementation
  Part: ECS
  Version:      Record Number: 20920
  Last Modified: 03/23/05 08:27:54
  Status: Active
        
                   
       Problem Description:

Keywords: input, output, icap, 32, 8

Urgency: Standard

General Description:
In the Xilinx Schematic Editor, the ICAP_VIRTEX4 symbol has an I and O
pin with a bus width of 8. The width should be 32.

Solution 1:

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 1.


Re: virtex4 reconfiguration time
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when

interpreted!

Howdy Stephane,

I have no idea how they really do it, but one simple way would be to
ignore the contents of D[31..8] until after you decide it should switch
to 32 bit mode:

32 bit mode          8 bit mode
 D32   D0             D32   D0
 XXXXXX32             XXXXXX08
[START 32 BIT MODE]   XXXXXXXX
 5678ABCD             XXXXXXXX
                      XXXXXXXX (or 08 could be here)
                      [START 8 BIT MODE CONFIGUATION]
                      XXXXXXCD
                      XXXXXXAB
                       ...etc

X's are obviously don't cares.

BTW, I neglected to mention something on my original reply about the
configuration time: it is only that low (10 msec) if you can really
feed a byte to the part on every clock cycle.  If you are driving the
selectMAP from a microprocessor, that may not be possible since it can
take them many cycles for each bus access.

   Marc


Re: virtex4 reconfiguration time

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Looks ok... I would have it done by myself if working for Xilinx ;-)

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Right! I did that with a spartan2, and [MV MV SUB BEQ] @11MHz led to a
700ms configuration time... awful, but this was not a big deal.


This time the idea is to use the ICAP port, when PR will be documented.
And you know what? The bottleneck will be the nor flash I'm reading from!

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Re: virtex4 reconfiguration time
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<snip>


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little bit


The SelectMAP configuration interface (Figure 2-11) provides an 8-bit
bidirectional data bus interface to the Virtex-4 configuration logic
that can be used for both configuration and readback. (For details,
refer to Chapter 8, "Readback and Configuration Verification.")

Regards,

John McCaskill


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