Virtex4: ISERDES -> FIFO -> BlockRAM fails

Hi all,

We are trying to do the same as in XAPP 704 in the simple examples. All on a Xilinx Virtex4 SX. We have LVDS inputs, ISERDES, a FIFO, which is all fine. As soon as we try to connect the output of the FIFO with a BlockRAM, it cannot be mapped anymore. Funny enough, the placer complains about the ISERDES, although without the BlockRAM they are fine.

ERROR:Place:605 - I/O component "data_in_p" is associated with ILOGIC component "ADC_DATA_IN_inst/RX_CLK_AND_DAT_inst/ISERDES_inst_master_0" . These components have to be placed in the same I/O tile into adjacent locations. The following issue has been detected:

This structured logic must be placed in a specific relative placement form and with a specific alignment on the CLB-grid. Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked. The location, the logic would be locked to is not correctly aligned. The problem was found at component ADC_DATA_IN_inst/RX_CLK_AND_DAT_inst/ISERDES_inst_slave_0 that would have to be locked at site ILOGIC_X2Y39.

How can we store the input data from the FIFO into a BlockRAM? Could it be that the BlockRAM is to far away? Different clock region? Would another Buffer or FIFO in between help? Thanks for all suggestions.

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jobeck
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