Virtex4 FX12 dynamic clock divider

Hi everyone,

For my design, which is implemented in Virtex-4 FX12 (speed grade -10) I need to get an adjustable (in operation) clock of frequency 30 to 66 MHz with the smallest possible increments. On the board I have 100MHz oscillator from which I tried to get 400 MHz (the higher the frequency the smaller the clock adjusting increments) using EDK 8.1's DCM (CLKFX

4/1). From this DCM I also power the PPC at 200MHz (CLK2X). I coupled the 400MHz clock to clock divider using rising edge as a process reference and an integer counter. This configuration does NOT work. The first problem is the frequency - EDK can compile my design if I lower the frequency to 200MHz, which is unaceptable. The other problem is a structure of my clock divider - if I make a process with rising edge detection the clock divider can only be even (clock is always divided by a factor of two!). How to build a fast dual edge (DDR) clock divider in VHDL? Is there any other way to solve my problem?

Help wanted,

Guru

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Guru
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The best way to create clocks with tiny increments is using Direct Digital Synthesis (DDS), a.k.a. phase accumulation. You just build a long accumulator, clock it from your 100 MHz (200 MHz would be better), and you can get at its MSB any frequency you want with any granularity you want (I built a circuit with 1 Hz resolution, but you can also get

1 millihertz.) The catch is jitter. You will create an unavoidable worst-case jitter of one clock period (10 ns or 5 ns in your case.) Reducing that jitter is very complicated. Peter Alfke, Xilinx Applications
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Peter Alfke

Guru schrieb:

What is "smallest possible increment" If I spent a hell of stuff and money on it, I will have microhertz resolution with jitter down to a few picoseconds. Hey man, give us some numbers. Frequency resolution? Jitter?

Such a question from someone who calls himself Guru? ;-)

There are many ways to skin a cat. One way is to have two counters, on counting on the rising edge, the other on the falling edge. Combining the two outputs in a clever fasion in a LUT can work. Or routing a signal to an output pin, make a connection to another pin back into the FPGA makes it possible to use the output DDR Flipflops. If you have a spare MGT, you can use it to make a real high frequncy DDS.

Regards Falk

Reply to
Falk Brunner

Peter,

Original poster mentioned that he was using V4. Can he use the dynamic reconfiguration feature of the DCM? If memory serves this allows for changing the M and D values.

Regards, Erik.

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Erik Widding
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Erik Widding

I think he can, but this gets us into the subject that Falk addressed, and I was too polite to mention: Be more specific! What is "smallest possible?" How much jitter is acceptable? If you can tolerate jitter, DDS is unbeatable. M/D still leaves big holes... Peter Alfke

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Peter Alfke

Here are some more details: The output clock is used for CMOS imaging sensor. The input clock can be 200MHz (CLK2X from DCM0) Desired clock increment is about 1 MHz. Maximum jitter not specified.

2 DCMs free for now.

I think that DCM with dynamic FX ratios cannot produce such increments, because output frequency can only take fraction ratios according to input clock. I think DDS is the best solution for my problem. The open question is which frequency to take for input: 100, 200, 300 ..MHz?

Thank you all,

Guru

Reply to
Guru

it is possible to have virtual clock DDS you can calculate several phaseses per highest useable clock (200MHz) and use one output stage that combines the result, IO DDR primitive, you can so have DDS clock as if it would be 400MHz while still using max 200MHz real clock in the FPGA

Antti

Reply to
Antti

Guru schrieb:

Ahhh, now we move forward!

Lets look at the worst case. You want 66 MHz max. If we use some kind of 660 MHz master clock, we will have 1/10 UI jitter. Not too bad, not too good. I guess for the CMOS image sensor the jitter wont hurt, since it is read like a ram array, isnt it? So what you need is a multiphase DDS using lets say 4 accus. The MSBs must be parallel-serial converted using a x2 Clock and a DDR output stage. Been there, done that. Do a search in the FPGA FAQ, its explained there.

Regards Falk

Reply to
Falk Brunner

Can IO DDR primitive output be used inside FPGA, because I need this clock also for several processes inside FPGA, or I have to route it to output I/O pin and then physically tie it to input I/O pin? By using DDR primitive I can theoretically get only 2.5ns jitter (+ logic delay) at 200 MHz input clock.

Guru

Reply to
Guru

Guru schrieb:

Hmmm? Maybe you can do a trick. Define an bidirectional inout port, drive the output with the DDR FF and use the input as the (generated) clock. This may work.

Logic delay doesnt matter for jitter, the delay is just a static phase shift. If you use a 300 MHz clock, you can go down to 1.6 ns. What device are you using? AFAIK Viertex-II etc. go up to 840 Mbit/s in DDR data transfer, Spartan-3 up to 622 Mbit/s.

Regards Falk

Reply to
Falk Brunner

I found DDS code in comp.arch.fpga archives:

library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all;

entity dds is generic( bits:natural); port( clk: in std_logic; inc: out std_logic_vector; clk_out: out std_logic);

end dds;

architecture RTL of dds is signal accum unsigned(bits-1 downto 0); begin

process(clk) begin if clk'event and clk='1' then accum

Reply to
Guru

Guru,

A five minute exercise with an excel spreadsheet is all it takes to come up with the answer to the DCM resolution question. If starting with a 66MHz input clock (which from the exercise became clear to me that one would want to use the top frequency of the range to get best resolution), you can get very close to your desired resolution. There will be steps of 1.06MHz going from M/D of 15/31 to 1/2 and from 1/2 to

16/31, so the worst two steps happen to be adjacent, and at the very low end of your frequency range. The next worst step pairs are 0.76MHz, 0.71MHz, and 0.53MHz and 0.57MHz.

The interesting thing to note is that the steps immediately prior and immediately after each of the worst case pairs are all on the order of

0.10MHz. So as a practical matter the DCM gets you extremely close. If your range of frequencies were just slightly less than 2:1 (i.e. 34MHz to 66MHz) you would be able to get a worst case 0.76MHz step size.

The DCM solution will drastically reduce the jitter. This may or may not be significant in your application. The M/D values will want to be stored in a look up table (i.e. a blockram).

Just more food for thought.

Regards, Erik.

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Erik Widding
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Reply to
Erik Widding

Thanks Erik,

I did my homework:

DDFS at 300MHz using DDR primitive has 1.67ns of jitter. The DDFS problem are high frequencies, where 1.67ns of resolution results in 66.6 to 60 increment (15 to 16.6ns). This is the are where I need the finest resolution. Another problem is building from a scratch - it takes lots of time.

I will use DCM_ADV solution with dynamic M/D. With one DCM I will produce 66.66MHz (100*4/6) which will be used as an input clock of DCM_ADV. To simplify the design I will lock the divider D to 32 (input

31) and change only the multiplier value from 12 to 32 (25 to 66.6 MHz). In this way I get 2.083MHz resolution (which I think is enough) in the whole range and only 0.5ns of jitter (according to Xilinx LogiCore calculation).

Thank you all,

Guru

Reply to
Guru

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