virtex4 distributed RAM

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Hi, I'm looking for Timing info on an Asynchronous FIFO built using Distributed
RAM on Virtex4. the part # we are using is : LX100-10, package FF1513. Xilinx
publishes the FIFO timing info for Asynchronous FIFOs using Block RAM, but not
distributed RAM. Specifically, I'd like to know the timing of all the FIFO
signals (FULL/EMPTY, ALMOST_FYLL/ALMOST_EMPTY and other FIFO status signals). If
someone could shed some light on where I might find this info, I'd really
appreciate it.

Re: virtex4 distributed RAM
Why do you want to use distributed RAM, when you can get a ready-made
high-performance FIFO in each BlockRAM? The timing is guaranteed for up
to 500 MHz clocks, even asynchronous ones.
What is it you are really after?
Peter Alfke (member of the V4 FIFO design team)

Ram wrote:
Quoted text here. Click to load it
Distributed RAM on Virtex4. the part # we are using is : LX100-10,
package FF1513. Xilinx publishes the FIFO timing info for Asynchronous
FIFOs using Block RAM, but not distributed RAM. Specifically, I'd like
to know the timing of all the FIFO signals (FULL/EMPTY,
ALMOST_FYLL/ALMOST_EMPTY and other FIFO status signals). If someone
could shed some light on where I might find this info, I'd really
appreciate it.


Re: virtex4 distributed RAM
Hello Peter, I changed my mind and am submitting two more questions here on
Virtex4 Async FIFO for you :

1. On the Coregen tool, we could not find a button to choose between First Word
Fall Through (FWFT) and Standard modes of operation

2. We have a file in our XilinxCoreLib directory called FIFO_GENERATOR_V1_1.v
and it does not seem to understand FWFT either. is there a newer version of this
file as well as Coregen/Fifogen tool that we need to upgrade to to get these
features ?

Thanks

Re: virtex4 distributed RAM
Are you run out of block RAMs?

Quoted text here. Click to load it
Distributed RAM on Virtex4. the part # we are using is : LX100-10, package
FF1513. Xilinx publishes the FIFO timing info for Asynchronous FIFOs using
Block RAM, but not distributed RAM. Specifically, I'd like to know the
timing of all the FIFO signals (FULL/EMPTY, ALMOST_FYLL/ALMOST_EMPTY and
other FIFO status signals). If someone could shed some light on where I
might find this info, I'd really appreciate it.



Re: virtex4 distributed RAM
Nope, please see my response to Peter Alfke in this forum

Re: virtex4 distributed RAM
Thank you for your quick response Peter. I'm not saying that we are going to use
distributed RAM, infact we are going to use Block RAMs just as you pointed out.
But, since Coregen generates Async or Sync FIFO based on either RAM, I was
curious to know what the Timing model was if we ever have to use distributed RAM
based FIFOs in the future. If you have any info on this I'd very much appreciate
it.

I have a few more questions on the Block RAM FIFO but, I will address them
through Webcase.

As an aside, I remember you from my AMD days way back in 1983-84 timeframe. I
was in Clive Ghest/Steve Dines organization working on the QPDM graphics
processor.

Thanks.

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