Hello,
I'm trying to use a slightly unconventional way of configuring a Xilinx Virtex4 FPGA that as far as I can tell should work, but doesn't. The plan involves using a microcontroller to place an atmel serial flash into continuous read mode, and then relinquish control of the flash's clock and data output lines to the FPGA, and finally release INIT. The FPGA, set to Master Serial mode, then begins clocking the data out of the flash as if it were clocking out of a xilinx PROM.
It all seems to work the way it should -- the right data appears on the data line -- but DONE never goes high, it just keeps clocking as if it's not getting any data. The one difference between the flash and a xilinx PROM is that the flash outputs data on the falling edge of the clock, while the PROM outputs on the rising edge. And indeed, if I place an inverter in line with CCLK, the configuration works fine.
I don't understand why the clock polarity is causing a problem given that the FPGA supposedly samples on the rise of CCLK. On the rise of CCLK, the data out of the flash has been stable for a full cycle, having changed on the fall of CCLK.
Anyone know what I'm missing?
Mike.