Virtex4 CLKX2 DCM Jitter

I guess this is really one for Austin, but I wonder if anyone else has any input.

My company supplys a design which is used in a V4LX25. The design uses external QDR SRAM @ 200MHz (400MBit). The design has a built in memory test which exercises the memories under worst case conditions (flat out) with pseudo random address/data, and all works well. However, the jitter on the Kclock to the memories gets a lot higher (>600pS) when this test is running. When the system is idle the jitter is

Reply to
MikeJ
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MikeJ,

Let me study this, and get back to you.

Austin

Reply to
austin

Answered off-line,

Lots of stuff to go over.

Xapp 623 is the start of the process of review.

If IOs are causing it, then decoupling of the IOs, and ground bounce, is critical.

Austin

Reply to
austin

Thanks Austin, /Mike

Reply to
MikeJ

And one technique that Xilinx recommends for lessening effects of ground bounce is to drive unused adjacent IO to GND on the PWB, and drive these as outputs on the FPGA. ie tie the input to the obuf to logic 0. Regards, John Retta Retta Technical Consulting Inc. Colorado Based Xilinx Consultant

email : snipped-for-privacy@rtc-inc.com web :

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Reply to
John Retta

Mike,

Assuming you've already checked the likely suspects, here are some random thoughts on jitter troubleshooting. (FWIW, many of these will break other things and are not suggested as a fix, just a troubleshooting aid )

A) Try to distinguish whether the DCM input clock is affected when the I/O switches; or, if the DCM itself is being affected; or, if both are

- clock your DDR clock forwarding flop directly from the input clock, with no DCM: does it still get the jitters when the QDR I/O switching starts?

i.e. 100 Mhz input clock -> BUFG -> DDR output

( IIRC, you don't need to fiddle with DIFF_OUT buffers for global clock forwarding in V4 due to the already differential global clock distribution )

- if you have another clock input ( esp. in a quiet bank ), temporarily clock the QDR logic from that ( with and without DCM ) and see if the jitter changes

B) DCM Duct Tape

- LOC the DCM to the other DCM sites on the chip; see if that affects the jitter

Even if it's not an optimum LOC for the DCM because of the GCLK pin location, and there needs to be a long clock route to get there, putting the DCM on the other side of the chip away from I/O activity may help your jitter ( but not meet system timing )

- change FACTORY_JF as described in Answer Record 13756

If decide to try CLKFX, see AR 21594 and AR 18181 ( V2/S3 era advice, not sure how it applies to V4 )

- change DCM DESKEW_ADJUST to SOURCE_SYNCHRONOUS to turn off the internal DCM feedback delay element (more V2 era advice) ( see pages 4-5 of XAPP259 )

Other questions:

- Do you have any spare LVDS input/outputs elsewhere on the chip ? ( handy for clock troubleshooting )

- If you run a 'hammer' test 0000 FFFF instead of pseudorandom patterns on the QDR address/data lines, does the jitter get much worse and/or the DCM unlock ? ( also try changing the toggle rate, 1,2..N clocks )

FWIW, my S3 Starter Kit SRAM memory test that used a x2 DCM would unlock on hammer patterns, even with slow slew I/O meeting SSO limits, unless the DCM was LOC'd to the other side of the chip away from the SRAM I/O.

- Is the QDR interface bandwidth sufficient to allow for Asteroids vector generator emulation at 1080p resolution?

Brian

Reply to
Brian Davis

Why, are we chopped liver?

Reply to
mk

Hi John,

Yes, I have done this before on the bigger packages - any spare pins get nailed low. This is a ff668 device and sadly I haven't got the spare pins. All IOs are HSTL class I and the tools say I am within the SSO limits .. Investigating the PDS and layer stackup but it looks pretty good to be honest. Cheers, /Mike

Reply to
MikeJ

Linear regulators get rid of noise below c.100kHz. Above that frequency, the only attenuation you get is the resistive loss with the bypass caps. I imagine your jitter is somewhat higher than 100kHz, so you might get more joy (and save $£?¥) using passive filtering. Certainly, you must keep VCCAUX separate from the Vcco 2.5V. HTH, Syms.

Reply to
Symon

Hi Brian, thanks for your tips.

Measurements at the clock input balls show no significant increase in jitter.

Good idea. I tried this before and I will need to repeat it to be sure. I fed in a 200MHz single ended clock of the correct phase into a spare input pin and fed this through the same path minus the DCM. It looked ok which pointed me at the DCM but I need to go back to this.

Also interesting is the other outputs (Address, data etc) show a much smaller jitter increase.

good idea.

Tried both of these. CLKFX looks about the same, but the "shape" of the jitter is slightly different. Austin assures me that in V4 the DCM is much less susceptible to noise than in the V2 days - I've been through this before :)

I have an unused bank with 2V5 IO actually so I could possibly get some clocks in and out here.

mmm. The chip actually has a max switching test as well which works (so no DCM unlock). I will make some measurements.

I usually try and keep work and the games separate, but it would make an excellent platform and save me finishing the DDR controller !! I have a broadcast serial digital 720P output module somewhere, but what I need to make is a DVI output I think ....

Thanks for all the tips people, I will get some more measurements over the next week or two. Thanks also to Xilinx for the support.

My gut feeling is it must be a weakness in the PDS which is effecting the DCM particularly, but measuring these things is certainly tricky.

Cheers, Mike.

Reply to
MikeJ

There is a single VCCIO 2V5 bank on the device but it is totally unused. My thoughts on the regulator were to isolate the VCCAUX from possible noise elsewhere on the board. (I remember linear regs were recommended on the SerDes 2v5 supplies on Virtex2pro)

I will improve the layout and filter the VCCAUX supply and have a small well bypassed area fill for it.

Regards, Mike

Reply to
MikeJ

mk,

Well, you may have whatever opinion of yourself you desire, and I can't control that.

I just had a series of questions and comments, and the poster had emailed me directly, so I offered him the courtesy of a personal reply.

His issue is IO switching, and it isn't a question of not working, it works just fine. He has customers who are nervous when they see jitter (seems a redundant sentence?), so he needs to find his margin, prove he is OK, or reduce the jitter (again, only for cosmetic reasons).

The extra pins to ground isn't go to do anything for him (use of IOs as ground), as he is already in an excellent package in V4, and we are looking at his bypassing solution. He used all one value for Vcco bypass, 0402 1.0uF, and I am working on showing him that there can be anti-resonant peaks (right around 200 MHz), where the use of all one value is a bad choice.

"Chopped liver?" I wonder where that came from?

Austin

Reply to
austin

Hi Austin, Anti-resonant peaks? Right around 200MHz? With a 1uF cap? Wow, I'm sure looking forward to you posting what your advice is. You sure you've not been spending too much time in the Gaslamp Quarter? ;-) Cheers, Syms.

Reply to
Symon

Symon,

Gaslamp? Nope, although right around the block, on Front Street is our vacation residence. Right now I am at the Hyatt, on the bay, up the street from the convention center.

Great show, all those booths with Xilinx products. Wow. Seems like any booth I go to, they are selling, supporting, using, or in some other way, merchandising Xilinx.

A little disappointed at how there is so little competition. How are we going to keep our edge?

John Daane this AM announced that they will have a 45 nm product in

2008... Perhaps they will skip 65nm altogether? "Fast follower"? I am shocked. Their 65nm S3 is announced to be released in August, 2007.

Perhaps everyone should wait until 2008, and get their 45nm?

Of course, TSMC is making a huge splash at DAC with their 65/45nm tools, process, and IP. Too bad it is the "cell phone low power" processes they are pushing. In talking to ASIC designers (lots of those at this little show), they are frantic about the poor models, lack of process control, huge variations, and inability to design for low power. With the "low power process." Too bad if you want a high performance process at 65 (or 45nm). At $2M a mask set, "guess and check" gets pretty expensive!

I also learned the ASIC emulation business is estimated to be $30M to $40M a year (FPGA Journal story today), so compare that with last year's sales for Xilinx (1.8 billion $), and you see just how IMPORTANT those ASIC simulation sockets are.

Don't get me wrong, we love that business, because it is the largest parts (xc5vlx330), and we have no competition for more than one year now ... so we "own" the entire market (no competition). But owning the "high ground" is not much money when you look at it compared to the overall sales numbers.

But, I digress.

We have seen where the various parasitic inductances, and the capacitance combine to create spots where there is no effective bypassing at all. Hence the need for more than one value to "break it up."

More later, I have asked one of my SI gurus to put something together to illustrate the (potential) problem.

Austin

Reply to
austin

This is proof that East Coast Jewish facetiousness just doesn't come across correctly on Usenet. Proper pronunciation: Borscht belt comedian.

"What am I, chopped liver?" is a gentle nudge meaning, "please don't ignore me!" (or less gently, depending on tone-of-voice, "Thanks for ignoring me ...")

In this context, an issue was raised in public but answered off-line. Hence, the nudge.

-a

Reply to
Andy Peters

I was as confused as Austin for a while, but it turns out Jewish folk help us gentiles by posting on Wikipedia! :-)

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Cheers, Syms.

Reply to
Symon

This is an older document, but has some very good Graphs of Decoupling networks :

Atmel's "EMC Improvement Guidelines" :

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I've also seen more recent papers, pushing the "wider aspect ratio" caps, and the pass-thru decouplers, that give T networks, and some of those include PCB Plane impedance plots.

Q: what is the package capacitance / impedance of the present FPGA packages alone (no decoupling), and of the FPGA mounted on a typical planed PCB (no caps) ?

-jg

Reply to
Jim Granville

Hi Jim, Thanks for the link, you're dead right. Also, on Murata's website, they give away some cool tools for their bypass caps which show their impedances. I'm interested how to get a resonance at 200MHz with a 1uF cap. Just to check,

200Mhz = 2*10E8, right? W=1/sqrt(1/LC) Hmmmm.

As for your question, dunno, but I'm pretty sure, Xilinx have put ceramic bypass caps inside the package. It won't work otherwise.

Cheers, Syms. p.s.

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Reply to
Symon

Whoops, W=sqrt(1/LC)

Reply to
Symon

OK, that'll be very interesting. I look forward to your guru's post. Many thanks, Symon.

Reply to
Symon

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