Virtex4 : cleaner signals?

Anyone have tips on having the Virtex 4 generate cleaner signals? I have 8 data lines coming out from the header IOs. They are supposed to be 3.3V but the noise amplitude swing is rather big, sometimes the high signal dips all the way to

2.1V.

I have slew rates set to fast, drive is 12. What can I do in the FPGA to improve signal quality?

Reply to
John
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John,

The closest to a 50 ohm nominal trace IO driver is LVTTL/LVCMOS 8 mA SLOW, or 6 mA FAST.

I suggest you simulate your signal integrity before doing anything.

It is the shortest, and easiest path (as well as being the safest).

Austin

Reply to
Austin

data lines coming out from the header IOs. They are supposed to be 3.3V but the noise amplitude swing is rather big, sometimes the high signal dips all the way to 2.1V.

improve signal quality?

It sounds like you have reflections on your 8 data lines, which means that your lines are not terminated properly. Try setting the slew rate to SLOW and the drive to the lowest current level you can get away with. This will lengthen the rise and fall times of the signals, which should help, but might not "fix" your problem. Read up on transmission lines and termination, and Signal Integrity (SI). I think there are APP notes on SI on Xilinx's web site, but I'm not sure.

HTH

-Dave Pollum

Reply to
Dave Pollum

You might also try changing your IO Standard to LVDCI (Low voltage Digitally Controlled Impedance). I've used this in the past to clean up my signals. Note, using this standard requires external reference resistors be connected to enable DCI. You'll have to check the board schematics usualy IO_,,,_VRP and IO_,,,_VRN on each FGPA bank.

Reply to
JuanC

Reply to
Peter Alfke

Hi John, Please don't take this the wrong way, but often if folks are just starting learning about SI, they also can make errors when probing the signals. Could you tell us how you know that the signal is doing as you say? For example, what 'scope setup do you have? Austin's advice is good; Hyperlynx has a great 'scope! :-) HTH, Syms.

Reply to
Symon

And it's a steal at $47,500 per seat! What is the cheapest way into HyperLynx?

Reply to
Tim

I am using a digital scope and triggering on rising edge. I do a single sample and use two cursors to measure the reflection.

One side of the probe is on the pin, the other side is on ground.

BTW, 50 ohm source terminator cleaned up the data lines a lot (lowest it drops to now is 2.9V), but my 25mhz clock signal still has a lot of noise, since I didn't design my interface board to have a source terminator on the clock.

Reply to
John

Keep in mind that a single destination doesn't care about how the source looks as long as the destination looks clean.

It isn't clear from your description if you're talking about the source or the load.

Look only at the destination and report if your signal still looks unclean or if - remarkably - you suddenly see very nice transitions.

Reply to
John_H

Hi John, Check your probe is grounded correctly. The 6in wire with a croc clip doesn't cut it at today's rise times.

Look for "Sensitivity To The Probe Ground Wire" in this article.

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This guy has a cool website and shows you how to make your own probe in pictures! (I'm pretty sure I saw him once cycling the other way on the Los Gatos creek trail ["ON YOUR LEFT!"], but that's another story!)

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Also, there's a difference between noise and reflections. For example, if you use your digital scope in infinite persistence mode, noise will make all the traces get thicker vertically as the noise is not correlated to the clock signal you're measuring. On the other hand, reflections are the same for every clock cycle so the traces stay thin. It may help diagnose your problem if you can say which of these is your problem.

HTH, Syms.

Reply to
Symon

It is reflection and not noise, since it looks the same on every pulse.

I'm trying to use LVDCI_33 on my clock signal and LVTTL on my data lines. They're all on the same bank (7). It compiles and programs but I read there is only one IOSTANDARD allowed per bank? How come it still works?

Also, how much of a difference does it make where the source terminators are located? The board was designed with the source terminators closer to the destination rather than the source, unfortunately.

Thanks.

Reply to
John

It is reflection and not noise, since it looks the same on every pulse.

I'm trying to use LVDCI_33 on my clock signal and LVTTL on my data lines. They're all on the same bank (7). It compiles and programs but I read there is only one IOSTANDARD allowed per bank? How come it still works?

Also, how much of a difference does it make where the source terminators are located? The interface board was designed with the source terminators closer to the destination rather than the source, unfortunately.

Thanks.

Reply to
John

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