Virtex II Slice Design - ARGH!

Hi, Why is it that you cant put a FDRE and an SRL16E on the same slice? I looked at a V2 slice within FPGA Editor (woohoo, got the full version of ISE at last!) and it shows me there's a WE signal going to the SRL16, driven by the slice's SR input. Now why would you want to drive it with the SR input when there's already a CE input available??? I wanted to construct a delay line (SRL16 + FF), whose output FF can be reset but then this is not allowed. Any workarounds? Thanks. -Jim

Reply to
Jim George
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Hello, while I have no answer to your question, I was intrigued enough to play around in the FPGA editor for some (too long) time.

One way to approach this problem is to try and free the BY input, which I assume is used as DI input of site G (through the DIG_MUX). If BY can be freed, it can be used for REV of the FFX and FFY. Now, one can not use the ALTDIG input with a shift register (why?), leaving only SHIFTIN as a candidate.

Paradoxally it may be possible to construct a delay line "SRL32+FF" by placement of a SRL16 in RLOC X0Y1 BEL constraint "F", which shifts out to a SRL16 cascaded in RLOC X0Y0 BEL constraint "G". The output of this second SRL16 goes to FFY. The input to this SRL32+FF is to BX of RLOC X0Y1 BEL "F".

Intrigued, Nossum

Reply to
Nossum

If you need to reset the flop, use an external flop. You can still pipe the SRL through the non-reset flop if your shift clock is so fast you can't tolerate the clock-to-Q plus routing for the final, external, resettable flop.

Reply to
John_H

Nossum, I too am puzzled why we cant use ALTDIG as an input for an SRL16. SHIFTIN is meant as a "carry" input from another SRL16, it's a dedicated line which doesnt go to the nearby switchbox, so that's out too. Unless, like you said, I can use two SRL16s to form an "SRL32", which would free BX (which was DI of the SRL16 in LUT F). I guess this BX can then be used as a reset for FFX. John, I can tolerate the delay, I guess. I will be running the design at 65 MHz. The reason I cant use either this or John's suggestion of an external flop is that I want to pack this with as much density as I can (2 bits per slice). Sometimes the SLICE design of a Virtex just puzzles me! Thank you for the replies. -Jim

Reply to
Jim George

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If you need a common reset for a large number of SRLs - your density desires - you might get by with registering the reset signal and using it for qualification of the SRL flop outputs downstream. If your SRLs feed LUTs rather than other dedicated primitives and you don't use all the inputs to those LUTs, it would be simple to force an "effective" reset on those signals by masking the signals with the registered reset. Retiming. What fun!

Reply to
John_H

The LUT RAM (which came before the SRL) uses SR instead of CE for its write enable to allow packing a RAM and an FDE together in the same slice without forcing the RAM's WE to be tied to the FF's CE. When the SRL16 feature was added, its implemenation used the same basic "write" circuitry, so its CE became the same pin as the RAM's WE, namely SR. Thus, if you'd like to have an SRL driving a FDRE, you'll have to place them in different slices, as one poster already suggested.

As for ALTDIG driving SRLs... The LUT you see in FED is an abstraction. In silicon, there actually exists no path from the ALTDIG to the SRL's data input, nor is there a path from ALTSIN to the LUT RAM's data input.

One other point... the REV pin on the FFs should not be used without also using the SR pin. Using the REV pin to reset your FF while using the SR to do something unrelated (i.e. SRL CE) doesn't work.

Regards, Trevor Bauer Xilinx

Reply to
TJB

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