I'm trying to build a simple core in which decode and register file access occurs in the same cycle on a virtex II pro board.
Decode completes in the half clock cycle after the positive edge. Any ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge?
Thanks in advance
access occurs in the same cycle on a virtex II pro board.
ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge?
Ali, I suppose you want to use the dual=ported BlockRAM in Virtex-II. Those two ports are completely independent as far as addressing and control is concerned. They only share the data. So you can use one port to write on one clock edge, and use the other port to read out on the other (or the same) clock edge (or even use a completely different clock). The issue will be speed. You obviously should not try to read something that is not yet reliably stored in the data latches. So do a timing analysis. Our dual-ported BlockRAMs are really easy to understand, as long as you realize that the incoming Address, Data, and WE control are all registered. So nothing happens without a clock edge, even in read mode. That's desirable in many cases, not desirable in others, but it is "non-negotiable". Also, we throw in a read data output even when you write, and you can choose to read the old or the new data, or even to maintain the previous data on that output port. Now, if you want to use the LUTs as dual-ported RAM, then the structure is different, and you can read without using a clock edge. Peter Alfke, Xilinx Applications
For register file reads, why not access the BlockRAM with the lower address bits anyway and only "use" the result if the BlockRAM was selected? This assumes the register file is a contiguous chunk of memory and the read port wouldn't be needed for something else that cycle.
occurs in the same cycle on a virtex II pro board.
ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge?
Ali,
two ports of DPRAM block memory are completely independent, so the only thing you have to worry about is meeting the timing, in case the ports operate at a different clock edges.
Regards, Vladislav
occurs in the same cycle on a virtex II pro board.
ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge?
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