I've been playing with a test design consisting of a single 16x16=32 coregen generated multiplier with maximum pipelining and the registered output option. I am using ISE5.2 and I set the clk constraint to 200 MHz (and it is the only constraint). The results I am getting for different speed grades of the same XC2V2000 device are as follows:
6 - 4.986 ns 5 - 4.910 ns 4 - 5.839 nsIt seems a little weird that the middle grade is faster... Any comments on that?
Also, is this pretty much the best I can get? I might need to do a design that will have to run at 210 MHz and I don't feel comfortable with these results. I know this topic has been discussed in the past but I could not find good conclusive numbers...
Thanks, /Mikhail