I tried the Xilinx support line Case # 503586 and haven't gotten a good answer so though I would try here.
I am trying to interface to a ZBT SRAM from a Virtex II and was trying to do like in xapp 136 which used 2 DCM's to generate a internal FPGA and an external board clock using external DCM feedback that are aligned. That configuration in simulation (5.2i sp3) shows the external clock is .5ns delayed from the internal clock. We actually need to use a third DCM FX output to generate the clock for the SRAM. When we do that the external clock is now leading the internal clock by 1 ns. I didn't understand why what clock feeds both DCM's would change the timing and since our timing is tight I need them to be closely aligned.
The external clock is output using a DDR FF and I used the DCM wizard which should of put in all the problem bufg/ibufg etc which the V2 users guide says are needed if it is going to compensate for the pad to DCM delay.
I also think only 2 DCM's are needed, 1 to generate the internal clock using FX and a second to generate the deskewed external clock. That configuration seems to generate the same timing as the 3 DCM version.
Anybody know the correct solution?
Also does anybody know an easy way on the board to measure the alignment between an internal and external clock? Bringing the internal clock out to a pin would require knowing the actual loaded buffer delay which I wouldn't think I could get very accurate. If I can accurately measure it and its not a simulation artifact I should be able to tweak the phase shift to make it align. I would think that should then be stable across boards.
Couple other questions, has anybody seen the hold time of the V2 IOB flip flops documented?
For the DCM is is ok to feed the locked from one into the reset of the next or do we need to hold the reset for at least 3 clocks? Different documentation shows different ways and the direct connection didn't work under 6.1 simulation.
Thanks, David Gesswein