Virtex DCM phase alignment and CLK2X registering

Howdy Stephane,

There is no such thing as "perfectly aligned" in the real world! :-) The datasheet specs "CLKOUT_PHASE", the phase offset between any DCM outputs, just for this.

In general though, Xilnx says that you can treat the phase alignment of the outputs as close enough that you can transfer data between them. Many people, myself included, have succesfully done just that. There have been a few reports of problems doing this when there is extra jitter on the input clock, or even jitter induced from nearby pins.

Since CLK0 doesn't change on the falling edge of CLK2X, how about using that falling edge to sample CLK0 and determine its phase?

Try it and see what the tools say - that's what timing analyzer is for. When a clock goes to non-clock destinations, I believe you have the same guarantees as general logic: no hold time problems. But with the global clock delay as large as it is on the V4, I'm a little curious if that's still the case.

If it is an option, generating the clock enable with a toggling flop in the CLK2X domain from the start is the best option. Then there is no chance of prop delay, setup, or hold time issues.

Have fun,

Marc