Virtex 5 Rocket IO design for reading in ADC data.

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I am slightly confused as you are talking about LVDS and Rocket IO which are not the same. Usually with ADC designs you would input the LVDS signals from the ADC into the FPGA and use the ISERDES block clocked from the ADC clock. You may also have to use some soft of calibartion scheme involving an IDELAY block to ensure all bits are synchronised.

Jon

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Hello Jon,

I have output LVDS drive on my asic chip which I am then interfacing to the rocket IOs of the FPGA. Sorry for the confusion. So you are saying thou that I should not try any clock recoverary but just the clock from my asic? Is there anything else I would need to know to get this working properly?

Thanks so much

Jgk

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I am even more confused now as first you say you have an ADC and now you say an ASIC. I think you need to specify exactly what you have. Is it an ADC from say TI or is it a custom ASIC chip? Rocket IO do not even use LVDS type signals so I dont really see what you are trying to do.

Jon

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Hello Jon,

I designed a custom ASIC sigma delta ADC and i do not decimate on chip. so thus my data is coming out on 4 bits at 250MHz (clocked at 500MHz). On my ASIC, i designed custom 1.2V LVDS drivers that need a 100ohm termination off chip. I am using the rocket IOs and terminating them internally by programming them to have 100Ohm termination. I then set the rocket IOs to be lvds standard inputs.... which I think is correct to read in my data. I have to use the rocket IOs since my data is at 250MHz.....clocked at

Is that alittle bit more clear?

Jgk

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You would normally use Rocket IO for signals that are in the GHz range. LVDS on a Virtex 5 would easily handle a 250 MHz signal. Take a look at the Xilinx website as they have some application notes on interfacing ADCs. You do not want to be using Rocket IO for this type of application.

Jon

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Hello Jon,

So I do understand that 250MHz isn't fast, and the rocket IOs operate up to

When you say that LVDS on the virtex 5 could easily be handled at 250MHz would I then need a core clock at above 250MHz? Also what is hte max LVDS could be used on the virtex 5 without the rocket IOs? Can i use LVDS at

Jgk

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It seem to me as though you dont really understand the Virtex 5 architecture. You need to read the user guide and data sheet to get a feel what is possible with a certain IO technology. Rocket IO uses CML type drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible.

Jon

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Hello Jon,

You are completely correct, I do not understand the virtex 5 at all!! What guide(since there are like 10) would you recommend reading to learn about LVDS. Thank god i pinned out almost everything on my PCB to headers... just need to make a new socket board!

Thanks

Jgk

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Just go to the Virtex 5 documentation page. There is the User Guide which will give you info about all the tech inside the fpga. The data sheet will tell you how fast things can go. I have just had a look on Xilinx and there is an app note called

Virtex-5 FPGA Interface to a JESD204A Compliant ADC

It looks like you can use Rocket IO if your ADC is compliant to JESD204A standard. But as you have LVDS signals then you cant use this method.

Jon

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Go through the Virtex-5 user guide i.e. UG190. There is a detailed chapter on SelectIO (Chapter 6) which will help you in serialization/ de-serialization of your 250MHz LVDS lines. One important point to be noted here is that GTPs won't work at lower frequencies (You need to use the oversampling circuitry available in GTPs) like 250 MHz in your case. . Anyway GTPs work with HSTL standard which is different from LVDS.

For our 5Gsps PCIe Digitizers we use a Virtex-5 to read ADC-Data at

Virtex-6 or Virtex-6 should be able to do higher rates.

See xapp860.pdf and xapp855.pdf for more.

Kolja Sulimma cr> When you say that LVDS on the virtex 5 could easily be handled at 250MHz

VDS