Virtex-5 LXT launched today !

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already pricing given for 1000qty not bad at all.

unfortunatly the LXT related user guides ug194 EMAC ug196 GTP ug197 PCIe

are all deadlinks at the moment but hopefully those documents become available shortly.

new eval boards (besides ML501) are

ML505 - allows PCIe testing ML523 - GTP characterization board ML555 - 8x PCIe card

GTP has OOB support for PCIe/SATA and supports spread spectrum clocking as well.

Antti

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Antti
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Antti schrieb:

correction ug194 and ug196 are already available (appearead 6 minutes after the post), so the only missing one is the PCIe UG

myself

Reply to
Antti

Hmmm, first in industry with built-in PCI-express? Lattice SCM devices have built-in PCI express, have had since Feb (along with a boat-load of other stuff too). 100mW per channel, finally catching up with Altera and Lattice... S3A may have built-in Flash...seen that before too. It's kinda fun watching Xilinx playing catch-up.... ;)

Antti wrote:

Reply to
ddrinkard

Built-in PCIe or built-in SERDES?

Reply to
John_H

dd,

Hardened PCIe (in V5). Not a core. Don't see any hardened PCIe on Lattice website. Am I missing something?

Not that the Lattice SC products are not nice, they are, and I have acknowledged that a long time ago. But I don't see any hardened PCIe core(s). Is this something they are keeping secret?

Aust> Hmmm, first in industry with built-in PCI-express? Lattice SCM devices

Reply to
Austin Lesea

The Lattice parts have hard IP for the MAC and LTSSM (MACO), I'll look more deeply into the LXT, complete endpoint huh? I suppose that has some value. (is this where I'm supposed to cry Uncle?) One might assert it's splitting hairs suggesting other players have nada...but marketing is marketing...and Xilinx didn't get to be a billion dollar company by doing it badly....Since Xilinx is the only one talking about their 65nm products I suppose they are, by default, the defacto leader in that arena.

I just wanted to point out that the LXT is not the first FPGA with hardened communications IP blocks, that's all. Sorry to have ruffled your feathers. Those Xilinx parts, they're pretty nice too....and I acknowledged that a long time ago.... ;)

Aust> dd,

Reply to
ddrinkard

Austin Lesea schrieb:

MACO

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1GbE,10GbE,PCIe,SPI4.2

flexiPCS

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page 7

Lattice and Xilinx have a little different approuches.

Lattice has not full PCIe endpoint in any of the FPGA's but Lattice was the first to have FPGA's with hard-macro support for PCIe, the level of functionality being implemented in hard block is different (smaller part is hardened)

Xilinx full PCIe endpoint as hardblock is really qute. It solves the missing 5V PCI issue :)

Antti

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Antti

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Aurelian Lazarut

Aurelian Lazarut schrieb:

Aurash,

correct would be

built in PCIe compliant SERDES AND PCIe endpoint

if PCIe host or hub is required then it must be implemented 100% in FPGA fabric, eg full soft-core

Antti

Reply to
Antti

I *was* asking ddrinkard about the Lattice parts. I had forgotten about the MACO since my recent attention has been on the ECP2M devices.

Yes, the new Xilinx parts do the endpoint *and* the SERDES. That's what started the conversation.

Aurelian Lazarut wrote:

Reply to
John_H

Antti, Agree 100%, maybe it worth to be mentioned that SERDES is PCIe compliant but not only, when we say "PCIe compliant SERDES" some users will assume dedicated ser/des is for PCIe only, which is not the case, users have the freedom to program the MGTs in many other standards (it's more like, PCIe capable MGTs)

Aurash

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Reply to
Aurelian Lazarut

dd,

No ruffled feathers, I assure you. Just thought I might have missed something.

Marketing hyperbole aside.

Aust> The Lattice parts have hard IP for the MAC and LTSSM (MACO), I'll look

Reply to
Austin Lesea

so can anyone tell me what this means? what can I save from that?

right now one could use a virtex4 and buy a PCIe core. The plda solution eats up half of your FPGA and takes >1h just for synthesis ... This is not very flexible :-/

How much logic ressources will be needed with Virtex5 LXT? will there be any software support? drivers?

.. so the LXT parts have serdes? so I could do other high speed signals with that as well? or will there be a FX part in the future with real RocketIOs? I saw a V5 HD-SDI board at the xilinx booth at IBC last month - they didn't want to tell me much about it ... the announcement was close was that with LXT? or even FX?

bye, Michael

Reply to
Michael Schöberl

Michael Sch=F6berl schrieb:

all "T" parts eg LXT, SXT, FXT have the same serdes.

100MBit/s to 3.2GBit/s analog PLL (was not there before more flexible) supports spread spectrum clocking OOB support for at least SATA and PCIe (maybe other as well)

LUT requirement to implement PCIe endpoint in V5xxT : 100 LUTs

Antti

Reply to
Antti

Hmmm,

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"search" on "ML505" returns 0 results... these boards sound interesting though!

- Brian

Reply to
Brian Drummond

Brian Drummond schrieb:

you didnt look deep enough :) ok here is the link

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end of page, all 3 boards listed

Antti

Reply to
Antti

or Google didn't :)

Thanks! I guess we just have to wait a little longer for real information...

- Brian

Reply to
Brian Drummond

Brian Drummond schrieb:

the main features of 4xx and 5xx boards should be fairly similar so you can look at 405, 423, 455 documentation, to have approx idea what featueres each board has

ML505 should be fairly same as ML501 as the same reference designs work on both (except the GTP stuff) - ML505 has some knobs replaced by rotary encoder I think.

Antti

Reply to
Antti

I have seen a picture and specs of the ML555 and looks not a bad board but I am sure we can do better. Anyone with particular feature wants let us know before we get as far as the launch and they might get included.

John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board.

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John Adair

John Adair schrieb:

I am sure. We can do it better. Anytime.

100%

Antti

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Antti

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