Virtex-5, DDR2 SRAM, and ISERDES

Is it not recommended to use the ISERDES in the Virtex-5 to perform strobe-based read capture from a DDR2 SRAM (not QDR) part? I'm routing my echo clock (CQ) into the FPGA through an IODELAY component, then BUFIOs, and then straight to the 18 DQ pins (ISERDES blocks) using local clock routing. I'm seeing random bit errors that I attribute to the read capture path. Based on the errors, I think it might have something to do with the CQ and CLK phase relationship, but I'm not sure. I'm calibrating the read path using the 3 stage technique described in XAPP858. I'm seeing some good valid windows delaying my individual DQ data variably. I'm not getting any errors when I delay the DQ and CQ in lock-step in phase 2.

I just looked at the RTL vhdl code generated by the MIG for a DDR2 SDRAM controller and found that the ISERDES aren't used. Instead, the data is clocked in by an IDDR flop, and then directly into carefully placed fabric flip-flops (using a phenomenal number of directed routing constraint attributes).

Could someone explain to me when using ISERDES for strobe-based read capture is applicable, versus using the IDDR + hand-placed fabric flip- flops?

Thank you.

-Petersen Curt

I've only used the DDR2-SDRAM-Core, and there you can select if you want to use ISERDES or not. Don't know if this applies to the DDR2-SRAM-core as well.

As to why the ISERDES aren't used in the DDR2-SRAM-code from MiG I can only speculate:

If you want to use ISERDES, you need the clocks returned from the memory device connected to the right (i.e. clock capable) pins, plus the corresponding data bits need to be connected to FPGA pins in the same clock region (as obviuosly is the case on your board). This can make board layout more complicated, you might run into problems with the SSO threshold and so on. All in all, you're not as flexible. If you don't use the ISERDES, it pretty much doesn't matter which pins you use, even though the FPGA design is more complicated. This approach even works if you didn't think of the pinout constraints when designing the hardware.

I suspect the DDR2-SRAM-core originated in an xapp that was made for some Xilinx evaluation board that didn't use the right FPGA pins, so they had to do it this way. Or it was designed for older parts like Virtex2 Pro that don't have ISERDES anyway. They probably simply haven't had the time (or the incentive, i.e. a customer request) to "port" it to ISERDES.

For the DDR2-SDRAM-core the ISERDES-solution was released long after the other one as well. Maybe the application engineers can't keep up with guys that develop the new silicon :)

HTH, Sean