Virtex 5 announced

You can do it either way. For inferring code, you just have to pay attention to how many signals affect each flip-flop bit, and recode as necessary to keep that to the 4 inputs. It gets a little messier with clock enables and direct synchronous resets, as the synthesis tools tend to do with those what they like (the resets in Virtex-4, for example are dreadfully slow, so you want to keep the tool from using those, and in all cases you want to limit reset and ce inputs to registered signals). Managing the resets and clock enables in an inferred design often means using syn_keep directives to force a particular implementation.

You can also use instantiated LUTs or use an xc_map attribute on a separate entity representing the LUT logic to get a LUT primitive that you can add RLOCs to.

Reply to
Ray Andraka
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Hi Austin, I have some questions about the static power in Virtex 5. You said that the gate leakage is same for V4 and V5. Could you tell me how is the sub-threshold leakage in Virtex 5? I have read that subthreshold leakage will increase at 65nm (distance between source and drain of transistor will decrease in 65nm). Also, Virtex 5 has lower effective voltage than Virtex 4 (1.2 V in V4 to 1.0 V in V5). This should increase the sub-threshold leakage (Vth would be more significant). Moreover, if we take same sized Virtex 4 and Virtex 5 (which I assume to mean as same number of CLBs), then number of gates in Virtex 5 would be higher than Virtex 4, which means more leakage.

I am trying to find out how the static power could be saved in going from 90nm to 65nm. Did Xilinx do something new to prevent sub-threshold leakage? Thanks, Love Singhal

Reply to
Love Singhal

Love Singhai,

What we are seeing is that the choice of using triple oxide at 65nm is again, a requirement.

To have 65nm low Vt (very leaky source drain, leaky gate), 65nm high Vt (less leaky source drain, just as leaky gate); medium oxide 90nm low Vt (less leaky source drain, very little leakage gate), medium oxide high Vt (even less leaky source-drain, very little gate leakage -- these are used for all config memory, and all pass-gates); and finally both low and high Vt thick oxide for IO (no leakage at all to speak of) provides the IC designer with the best choices where they are needed.

So, because we must use the low Vt 65nm and high Vt 65nm transistors for speed to achieve objectives, we end up with more static leakage for V5 than we would for V4.

By "more" I mean that for the same number of CLBs, we still are seeing less, but with 65nm, we are doubling the logic per square area, so the same area chip now sees a similar static current, which now varies much less over temperature as the gate leakage has no temperature dependency.

As an example, if a V4 chip is taken down to -40C (I grade, of course), it has practically no leakage at all!

But, take a V5 of the same area, and take it down to -40C, and the leakage is roughly the same as when it was at room temperature. At hot, it is more, but on par with a V4 when it was hot.

V4 was at 1.2V, V5 is at 1.0 volts (core), so the lower voltage on the core does help keep the leakage under control.

So, in summary, what Xilinx did was specify a triple oxide process to two foundries that allows designers to use the right transistor for the right job. The result is the worlds first 65nm FPGA which still provides for an overall static savings in power for function, and keeps on par with static power per area.

Dynamic power is 1.2 squared vs. 1.0 squared for voltage alone (3-0% less dynamic power) PLUS the use of low K for another ~ 5% less power (smaller C). The final dynamic power savings will be characterized and released with the new power estimation tools, as not all features have lo-K (for example, clock lines are near the top metal layers, which are not low-K).

I hope that answers your questions,

Aust> Hi Austin,

Reply to
Austin Lesea
30% less dynamic power from voltage, excuse the typo...

Aust> Love Singhai,

Reply to
Austin Lesea

Some real/actual numbers could be a good idea, as all the info released so far seems to skirt this issue very deliberately....

-jg

Reply to
Jim Granville

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