One last thought,
There are some that suspected we were close to an announcement, and decided to wind up the presses to spread forth much blather.
Too bad.
They are now left looking a bit foolish.
30% speedup today.
More density today.
Lower cost today.
Lower dynamic power, and equivalent static power, today.
Triple oxide (again) today. I don't think people really appreciate the triple oxide, and what it does for us: it allows us a third type of transistor which is optomized for stability (think about SEUs) for the config memory, and extremely low leakage, as well as for a optimized pass gates. This means we still have the lowest static leakage of anyone at both 90nm AND now at 65nm. Oh, there is NO 65nm FPGA, except ours.
The triple oxide process is something we pioneered with our fab partners. Read: both of them. Something that we can do, because our customers have chosen Xilinx, and made us large enough (read successful enough) to specify our own process to our fabrication partners! Think of that: what vendor has enough solid proven business to specify a process to more than one fab?
Imitation is the sincerest form of flattery, as STM now also has a triple oxide 90nm process. I am sure they will also offer it at 65nm, as they also realized how useful it was to their customers.
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is a little late to the game. They are just now advertising 90nm triple oxide (by next calender quarter). Too bad. Too little, too late. That is not even 'fast follower'. That is a really late entrance onto the world stage by the leading player!
Now, for the second time, we have brought out this fantastic new technology, again on two fabs at once. No tricks, and no area hungry or goofy circuits for "maybe saving power." Just good old straight-forward simple engineering: use the right transistors for the right job. No risk to the customer, as the triple oxide technology worked great in V4, and is working great again in V5.
Austin