Virtex 4 Power consumption

Can anyone give me an estimate of the max current a V4fx60 FPGA will draw for VCCINT @ 1.2v, & VCCAUX and VCCO @ 2.5v?

I am designing a board with 9 of them and need a rough idea of power required.

Any help would be appreciated.

Jason

Reply to
jason.stubbs
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Using the Xilinx XPower tool, you can get an estimate of the worst case power consumption. If you just crank in 1.2v for VCCINT and 2.5v for VCCO, then by a simple division, you could get the max current drawn by a V4FX60 FPGA for a specific design. Different designs will draw different amounts of current.

Amr

Reply to
Amora

XPower says I need a completely mapped NCD file to get started. I dont have anything from the FPGA designer that I can use yet.

Can I do anything without requiring the NCD file?

Jason

Reply to
jason.stubbs

Jason,

Use the on line power estimator tool.

Less accurate, but it should allow you to get a good feeling for the power needed for you design.

Aust> XPower says I need a completely mapped NCD file to get started. I dont

Reply to
Austin Lesea

Austin,

The online tool also requires details of the design that I dont have. Can you guide me in what I have to enter to estimate the worse case?

Thanks

Jason

Reply to
jason.stubbs

Jason,

The 'worst case'? For a FPGA the 'worst case' is probably something you don't even want to consider.

For example, if you put in all 100% of the CLB FF's toggling at 300 MHz, you are likely to see that the power required is so large that you can not heatsink the device (would melt the solder and fall off the pcb).

The power estimators need your case, not the 'worst case'.

Aust> Austin,

Reply to
Austin Lesea

Make some estimates or guesses. That will at least give you a number.

Then go back and change the numbers you aren't sure about. If the answer doesn't change much then don't worry much. If the answer depends a lot on your wild guesses then you have learned that you have to work on that part of the design so you will have meaningful numbers to feed to the power-estimator.

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Reply to
Hal Murray

In terms of "PVT" - Process, Voltage & Temperature : In the WPT currently you can, for V4 FX devices, vary Vccint and the ambient temperature. That partially addresses the "V" & "T".

On the "P" or process side here are a few guidelines :

- if you are at worst case process and worst case voltage (1.3 V) you should use a factor of 2.5.

- if you are at worst case process but at nominal voltage you should use a 2.0 factor.

Brendan

Reply to
Brendan Cullen

Hi Brendan,

When I enter 1.25V vs. 1.20V in WPT 4.1, I'm given 687 mW vs. 660 mW of VccInt static power for a LX80, in addition to the 234 mW of VccAux power.

Similarly, for some random amount of logic utlization, I get 2727 mW vs.

2618 mW of dynamic power.

It seems to me that all the tool is doing is increasing the V in P = VI. However, increasing V should (a) increase dynamic current draw roughly linearly and (b) increase sub-threshold leakage by the square of 1.25/1.2. Neither of these effects appear to be modeled.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis (at home)

Paul,

Since we power the pass gates from Vccaux through a band gap referenced supply for the entire interconnect, many simple minded formulas that you may come up with will not apply.

Aust> Hi Brendan,

Reply to
Austin Lesea

you

MHz,

can

WOW. Now I really want to try doing, and make the FPGA fall off the PCB. That would be really cool. In building my board, I have used 1A voltage regulators to be on the safe side. I have designed my board to be flexible with various designs.

I guess a question which Austin or other members could help answer would be, what should be the best closest worst case when a relevant design is implemented on the FPGA. Since right now, I cant think of any design which could require all the CLBs toggling at such a high frequency. So maybe a design with Microblaze and very intensive DSP tasks implemented on the FPGA. What could be the power consumption for that or some other more intensive design on an FPGA

The online tool does not really help if you are planning on getting the best perfomance yeild off the FPGA, and need to know the power constraints before hand.

-Yaju

have.

case?

Reply to
Yaju N

It's like asking what is the price of a car or a house or a meal or a shirt or a book. There is always a more than 10-to-1 range.

I think 1A is very stingy when you want to do fast DSP, where many nodes wiggle very fast. Try it out, and keep your options open. A 1.5 or 1.2-V AA battery is a convenient voltage source for trying it out. They give you >1A for an hour, enough time for some experiments. Peter Alfke, Xilinx

Reply to
Peter Alfke

Hi Austin,

referenced

you

Excuse my simple-mindedness, but I am having trouble understanding. You have no circuitry powered off the actual VccInt rail? Your routing buffers, LUTs, DSPs, RAMs and other hard-IP blocks do not use VccInt but rather run off the regulated VccAux-driven supply?

Yes, I will concur that simple rules-of-thumb are never quite true in practice, and depend on exact circuits used. But are you suggesting that your supply current doesn't change with voltage? At all?

Paul Leventis Altera Corp.

Reply to
Paul Leventis

Paul,

It does change (with V), as is shown by the predictor.

And yes, we do use Vccint. We also use Vccaux.

Nothing is ever as simple as it first seems.

The devil is in the details, and telling you how it works would just allow you to copy it, and improve your own estimator.

Aust> Hi Austin,

Reply to
Austin Lesea

I think the problem is that the worst case is so nasty that it isn't interesting.

Can you go backwards? How much power can you get rid of? How big a heat sink and/or fan are you going to have?

There isn't much need for a power supply to put out more than that. Maybe 2x or 10x if you want to run in short bursts.

Another approach is to look at several prototyping boards and see what they have. If you don't hear complaints about it here that's probably big enough.

You could also add some big connection points so at worst you can add wires over to an external power supply.

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The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.
Reply to
Hal Murray

Hi Austin,

I also tried using the power estimation tool on Xilinx' web site and ran into pretty much the same results as Paul described earlier in the thread. Specifically, I tried >10 different configurations with a V4 LX80 part; varying the following parameters (all "utilization" parameters were between low and medium values, Vccint was varied between 1.1V and

1.3V):

Vccint CLB Usage FIFO Usage RAM usage DSP block usage Amount of air flow

What I found is that for every "configuration" I tried the ratio of Vccint_new/Vccint_old was almost exactly equal (equal at least to the precision of a mW) to the ratio of Power_new/Power_old (where the Vccint values are between 1.1 and 1.3 and Power_{new,old} refers to only the power reported as dissipated on the Vccint rail.

Could you please shed some light on the behaviour described above? Are Paul and I simply doing something completely wrong with the power estimator?

In order to avoid coming off as simple minded, I will refrain from any speculation on my side.

Thanks, Ljubisa Bajic ATI Technologies

Reply to
Ljubisa Bajic

Hi Everyone,

Since, despite previously voicing opinions on the topic, Austin does not seem to be willing/interested to reply to my question, I would like to extend it to anyone at Xilinx, or in general anyone who might know the answer: Can anyone explain the results that are described in my previous posting in this thread?

Thanks in advance, Ljubisa Bajic ATI Technologies

Reply to
Ljubisa Bajic

Paul has a point when he says that changing Vccint should cause a change in Iccint. This is in our plans for the Web Power Tool (WPT). When we have sufficient silicon-based data we will add the appropriate modelling to the WPT.

Changing Vccint (in V4) does also affect the sub-threshold leakage current - though our measurements and analysis todate suggest it is not the simple square relationship that Paul suggests. Again - we are continuing with our analysis - which will be reflected in time in the WPT if (and only if) the effect is significant. (It's of no benefit to the WPT user for us to model current variations due to certain small effects if the normal variation from part to part will swamp such tiny improvements.)

Brendan

"Paul Leventis (at home)" wrote:

Reply to
Brendan Cullen

Hi Brendan, Austin and Everyone,

Thanks for addressing my question.

I would just like to add that I have been told in private communication that Austin was away on vacation and thus was unable to answer my initial question, so I would like to retract the (rash) statement I made in my last posting about him not responding.

Thanks for the info, Ljubisa

Brendan Cullen wrote:

change in

have

to the WPT.

current -

simple square

analysis -

effect is

current

part to

currently

temperature.

mW of

power.

mW vs.

= VI.

roughly

1.25/1.2.
Reply to
eternal_nan

Ljubisa,

No offense taken. I am pleased that your questions have been adequately addressed.

My niece had her wedding in Kauai over the weekend, so we flew out Friday morning, and flew back Monday.

Wasn't nearly long enough to be in paradise! But I am slightly more mellow than usual just due to the sun, beaches, good friends, family and a few glasses on champagne.

Aust> Hi Brendan, Austin and Everyone,

Reply to
Austin Lesea

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