Antti,
Was this in the software tools alone? Sounds like you tried it on a pcb?
In hardware the DCM can generate output clocks up to 450 MHz (-11) (we have seen it work up to 600 MHz, I think the -12 is going to get set at
500 MHz for all corners). All outputs.
LF mode max is 150 MHz for CLK0.
HF CLKFX max (for _MS_MAX) is set at 315 MHz primarily to meet the CLKFX jitter output max issue.
CLKFX actually also goes to well over 450 MHz, but the jitter at 450 MHz for some M and D values is more than 20%, which makes CLKFX less useful.
Basically, it is a way for us to gently suggest that CLKFX not get used at these high frequencies due to the increase in jitter.
This is no different that V2, or V2P, where the CLKFX output is not as "hot" as the DLL outputs.
We have many customers who evaluate their M, D CLKIN freq, CLKFX out jitter, and go beyond the datasheet limits, but I have to say that when they do that, they will always get the frequency (it will always function), but they have to accept the risk of having too much jitter (they need to be sure they have enough slack).
Some folks pass the output to an external PLL to clean up the CLKFX output before they use it (like an icst.com ics8745 PLL/quad driver -- output jitter is ~50 ps P-P with a CLKFX input!!!).
One last comment: the input restriction when operating in HF mode (>
120 MHz) is arbitrary: it can be less. The issue again is with jitter generated. And, also with testing every single possible input frequency and every possible M and D. (Would just take too long -- even though the device is all digital, can't sell what you don't test.)
The good news is that it is not a PLL. With a PLL, testing takes forever as the PLL must lock each time (and that takes a long time, compared to the all digital DCM). So the testing we do is only as extensive as the data sheet.
[To think about: With an M/D of 10 bits total, and lets us say going from 1 MHz to 500 MHz in 1 MHz steps, that is 2E19 choices, and we have
4 modes (another 2 bits), we get >2E31 possible tests. We have to whittle that down to something that can be done in 100 ms for production test, and something that can be done in a week or two in the lab (also automated) for characterization. Oh, and we have to do this with lots of CLBs toggling, and IOs switching, too. I once figured that if it took 10 ms to do each test (we lock, measure frequency and jitter) it would take .01*2E31 = 249 days to test.]
I suggest you try it (use FPGA editor to put in the M, D and mode you want). Then measure the output jitter. If it works, and meets your needs, you may email me directly to get a Xilinx Official "OK to use" statement (i.e. we will support you forever with that combination of Fin, M, D, on that part). There are just too many combinations to support them all!
I recognize there are 'Magic Numbers' that we all end up using, so there is not an infinite number of options that get used.
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Have fun.
Austin