Hi *,
I'm having a litte problem trying to understand some things regarding the ISERDES in Virtex-4-IOs.
Here's what I want to do:
We use a lot of ADS527X-ADCs from TI. Those parts output 12bit/sample via LVDS-DDR-links running at up to 480Mbit/s. Up to now, using Virtex-2 Pro, getting this into the FPGA is a little tricky (see xapp774). In short, the current way is to feed the serial data into two carefully hand-placed 6-bit-shift-registers that are clocked with 180-degrees shifted clocks, and read those shift registers out in parallel once all
12 bits have arrived. Takes quite a bit of hand-placement, you have to be careful which I/Os you use to connect the clocks and data, you need DCMs to do phase-shifting, etc. Kinf of tricky, but it works.Now we're about to switch to Virtex-4, and at first glance the ISERDES seems like the perfect thing to make it all easier. But the more I think about it the more problems arise.
First, since all signals coming from the ADCs are differential signals, I need to instantiate an IBUFDS for each one. Plus I need to assign the LVDS_25-IOSTANDARD-attribute to it, as well as the DIFFTM-attribute, since there are usually no external termination resistors on the board to save space.
The signal I get as output from the IBUFDS I can feed into an ISERDES. Since one ISERDES can only give me 6 bits in parallel, I need to use two ISERDES in Master-/Slave-mode, but then they can only give me 10bits instead of the 12 I actually get from the ADCs. So it's not going to work that way.
Someone here posted awhile back that they would simply feed the _n-signal in one ISERDES, the _p in another, and have them run at clocks shifted by 180 degrees. That way, each ISERDES would give me one
6-bit-nibble of my 12-bit data word, one the "even" bits, one the "odd" bits of my data word. Sounds pretty easy to do.But that would mean using the two signals from a differential pair as two separate single-ended signals. Kinda misses the whole point of using differential signaling in the first place...
The way I see it there are several problems with this approach:
- If I don't use an IBUFDS for the differential input signal, I can't turn on the differential termination, plus I can't set the I/O-standard to LVDS_25 (the tools simply ignore those settings for single-ended I/Os). Again, kind of takes away the advantage of using LVDS in the first place. If I do instantiate an IBUFDS to at least get termination and set the IO-standard, I can't access the _n and _p-signals to supply two separate ISERDES anymore, and I can't feed the IBUFDS-output-signal to two separate ISERDES either.
- If I use the two signals of a differential pair as two separate single-ended signals, what I/O standard do I assign to them? It would have to be something that can cope with the tiny little swing of an LVDS-signal. Looking at the datasheet, each line of a differential pair has a worst-case V(high) = 1.265V and V(low) = 1.140V, so I'd have to use LVCMOS_15 or something like that and pray that this works.
- To control the ADCs (reset, powerdown, serial interface for enabling test-modes etc.), I need an I/O-voltage of 3.3V. Normally it is not a problem to use LVDS_25-INPUTS in a bank that otherwise uses 3.3V-I/Os, since the differential input buffers are powered by Vccaux, which is availabe in all banks (at least that's how it is in Virtex2 Pro). But if I have to use e.g. LVCMOS_15 for the LVDS-inputs, I need to power the entire bank with 1.5V. Not only would that mean I need to supply yet ANOTHER voltage on the board (one that I wouldn't need otherwise), but it would also mean I'd waste most of an entire bank of I/Os I could've otherwise used to control the ADCs and do some other little things. I/Os are precious as well as the board space I'd need for an additional regulator.
So I'm not really comfortable with this approach...
The way I see it the only way to do it "properly" is doing it the way it was done in xapp774, which will take some effort "porting" it to Virtex-4.
Is there some more "elegant" way to do it? I'd hate to just not use the ISERDES, those things are way to kewl to waste... :)
Any suggestions?
cu, Sean