Hello,
I was just browsing the Xilinx Libraries Guide pdf in search of BUFT component. However, it is not mentioned anymore in the 'Virtex 4 Libraries Guide for HDL designs'. I was looking into them to optimize wide muxes and a bus traversing the complete FPGA fabric. Are tristates left out of the Virtex4? Is there an alternative? What could be the motivation for such an architectural change?
Best Regards, Koen.