Virtex 4 IDELAY implementation

Hi

I'm currently doing some tests on an ML461 board, using IDELAY t

shift in some DDR signals. I am shifting 80 signals in groups of 8 Unfortunately, some signals do not get shifted, i.e. some of th IDELAY module do not seem to respond to INC & CE. I'm seeing thi in chipscope. I have tried (1) instantiating a single IDELAYCTRL, the let the tool replicate the rest and (2) instantiating all IDELAYCTR and manually assigning them to the appropriate regions. It didn't help.

Has anyone encountered such behaviour

I also found this on the xilinx website

formatting link

Does this mean that I have to invert the clock going into the IDELA

block

Thanks in advanc

Reply to
kyeyk
Loading thread data ...

formatting link

This is one solution. The other solution is to constrain the design so that the IDELAY control signals meet the half clock period timing. Either way, you need to use separate timing contraints on the IDELAY control signals so the timing analyzer will correctly analyze the timing on those paths.

HTH, Jim

Reply to
Jim Wu

Hi Jim

Thanks for your suggestions. I tried inverting the clock and it no

works

Reply to
kyeyk

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.